View ADV7322_2021813.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

multiformat 11-bit hdtv video encoder preliminary technical data ADV7322 rev. pra information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features high definition input formats 16-, 24-bit (4:2:2, 4:4:4) parallel ycrcb fully compliant with smpte 274m (1080i, 1080p @ 74.25 mhz) smpte 296m (720p) smpte 240m (1035i) rgb in 3- 8-bit 4:4:4 input format hdtv rgb supported rgb, rgbhv other high definition formats using async timing mode enhanced definition input formats 8-, 16-, 24-bit (4:2:2, 4:4:4) parallel ycrcb smpte 293m (525p) bta t-1004 edtv2 (525p) itu-r bt.1358 (625p/525p) itu-r bt.1362 (625p/525p) rgb in 3- 8-bit 4:4:4 input format standard definition input formats ccir-656 4:2:2 8-bit or 16-bit parallel input high definition output formats yprpb hdtv (eia 770.3) rgb, rgbhv cgms-a (720p/1080i) enhanced definition output formats macrovision rev 1.2 (525p/625p) cgms-a (525p/625p) yprpb progressive scan (eia-770.1, eia-770.2) rgb, rgbhv standard definition output formats composite ntsc m/n composite pal m/n/ b/d/g/h/i, pal-60 smpte 170m ntsc-compatible composite video itu-r bt.470 pal-compatible composite video s-video (y/c) euroscart rgb component yprpb (betaca m, mii, smpte/ebu n10) macrovision rev 7.1.l1 cgms/wss closed captioning general features simultaneous sd/hd, ps/sd inputs and outputs oversampling up to 216 mhz programmable dac gain control sync outputs in all modes on-board voltage reference six 11-bit precision video dacs 2-wire serial i 2 c? interface, open-drain configuration dual i/o supply 2.5 v/3.3 v operation analog and digital supply 2.5 v on-board pll 64-lead lqfp package lead (pb)-free product applications evd players (enhanced versatile disk) sd/ps dvd recorders/players sd/progressive scan/hdtv display devices sd/hdtv set top boxes clkin_a clkin_b hsync vsync blank y7?y0 c7?c0 s7?s0 timing generator pll o v e r s a m p l i n g i 2 c interface d e m u x standard definition control block color control brightness dnr gamma programmable filters sd test pattern high definition control block hd test pattern color control adaptive filter ctrl sharpness filter programmable rgb matrix 11-bit dac 11-bit dac 11-bit dac 11-bit dac 11-bit dac 11-bit dac ADV7322 05067-001 figure 1. simplified functional block diagram general description the adv?7322 is a high speed, digital-to-analog encoder on a single monolithic chip. it includes six high speed video dacs with ttl compatible inputs. it has separate 8-, 16-, 24-bit input ports that accept data in high definition and/or standard definition video format. for all standards, external horizontal, vertical, and blanking signals or eav/sav timing codes control the insertion of appropriate synchronization signals into the digital data stream and therefore the output signal.
ADV7322 preliminary technical data rev. pra | page 2 of 88 table of contents specifications..................................................................................... 6 dynamic specifications ................................................................... 7 timing specifications....................................................................... 8 timing diagrams.............................................................................. 9 absolute maximum ratings.......................................................... 17 thermal characteristics ............................................................ 17 pin configuration and function descriptions........................... 18 typical performance characteristics ........................................... 20 mpu port description................................................................... 24 register access ................................................................................ 26 register programming............................................................... 26 subaddress register (sr7 to sr0) ............................................ 26 input configuration ....................................................................... 39 standard definition only.......................................................... 39 progressive scan only or hdtv only ................................... 39 simultaneous standard definition and progressive scan or hdtv .......................................................................................... 39 progressive scan at 27 mhz (dual edge) or 54 mhz ........... 40 features ............................................................................................ 42 output configuration................................................................ 42 hd async timing mode ........................................................... 43 hd timing reset........................................................................ 44 sd real-time control, subcarrier reset, and timing reset 44 reset sequence............................................................................ 46 sd vcr ff/rw sync................................................................. 46 vertical blanking interval ......................................................... 47 subcarrier frequency registers ................................................ 47 square pixel timing mode........................................................ 48 filters............................................................................................ 49 color controls and rgb matrix .............................................. 50 programmable dac gain control .......................................... 54 gamma correction .................................................................... 54 hd sharpness filter and adaptive filter controls ................ 56 hd sharpness filter and adaptive filter application examples...................................................................................... 57 sd digital noise reduction...................................................... 58 coring gain border ................................................................... 59 coring gain data ....................................................................... 59 dnr threshold .......................................................................... 59 border area ................................................................................. 59 block size control...................................................................... 59 dnr input select control......................................................... 59 dnr mode control ................................................................... 60 block offset control .................................................................. 60 sd active video edge ................................................................ 60 sav/eav step edge control .................................................... 60 board design and layout.............................................................. 62 dac termination and layout considerations ...................... 62 video output buffer and optional output filter.................. 62 pcb board layout...................................................................... 63 appendix 1copy generation management system .............. 65 ps cgms..................................................................................... 65 hd cgms................................................................................... 65 sd cgms .................................................................................... 65 function of cgms bits ............................................................. 65 cgms functionality.................................................................. 65 appendix 2sd wide screen signaling..................................... 68 appendix 3sd closed captioning ........................................... 69 appendix 4test patterns............................................................ 70 appendix 5sd timing modes .................................................. 73 mode 0 (ccir-656)slave option (timing register 0 tr0 = x x x x x 0 0 0) ......................................................................... 73 mode 0 (ccir-656)master option (timing register 0 tr0 = x x x x x 0 0 1)...................................................................... 74
preliminary technical data ADV7322 rev. pra | page 3 of 88 mode 1slave option (timing register 0 tr0 = x x x x x 0 1 0) .............................................................................................76 mode 1master option (timing register 0 tr0 = x x x x x 0 1 1)..........................................................................................77 mode 2 slave option (timing register 0 tr0 = x x x x x 1 0 0) .............................................................................................78 mode 2master option (timing register 0 tr0 = x x x x x 1 0 1)..........................................................................................79 mode 3master/slave option (timing register 0 tr0 = x x x x x 1 1 0 or x x x x x 1 1 1) ...........................................80 appendix 6hd timing ..............................................................81 appendix 7video output levels...............................................82 hd yprpb output levels...........................................................82 rgb output levels .....................................................................83 yprpb levelssmpte/ebu n10............................................84 appendix 8video standards ......................................................86 outline dimensions........................................................................88 ordering guide ...........................................................................88 revision history 9/04pra: preliminary version
ADV7322 preliminary technical data rev. pra | page 4 of 88 detailed features high definition programmable features (720p/1080i/1035i) 2 oversampling (148.5 mhz) internal test pattern generator color hatch, black bar, flat field/frame fully programmable ycrcb to rgb matrix gamma correction programmable adaptive filter control programmable sharpness filter control cgms-a (720p/1080i) enhanced definition programmable features (525p/625p) 8 oversampling (216 mhz output) internal test pattern generator color hatch, black bar, flat frame individual y and prpb output delay gamma correction programmable adaptive filter control fully programmable ycrcb to rgb matrix undershoot limiter macrovision rev 1.2 (525p/625p) cgms-a (525p/625p) standard definition programmable features 16 oversampling (216 mhz) internal test pattern generator color bars, black bar controlled edge rates for start and end of active video individual y and prpb output delay undershoot limiter gamma correction digital noise reduction (dnr) multiple chroma and luma filters luma-ssaf? filter with pr ogrammable gain/attenuation prpb ssaf? separate pedestal control on component and composite/s-video output vcr ff/rw sync mode macrovision rev 7.1.l1 cgms/wss closed captioning table 1. standards directly supported 1 resolution interlace/ prog. frame rate (hz) clk input (mhz) standard 720 480 i 29.97 27 itu-r bt.656 720 576 i 25 27 itu-r bt.656 720 480 i 29.97 24.54 ntsc square pixel 720 576 i 25 29.5 pal square pixel 720 483 p 59.94 27 smpte 293m 720 483 p 59.94 27 bta t-1004 720 483 p 59.94 27 itu-r bt.1358 720 576 p 50 27 itu-r bt.1358 720 483 p 59.94 27 itu-r bt.1362 720 576 p 50 27 itu-r bt.1362 30 74.25 1920 1035 i 29.97 74.1758 smpte 240m 60, 50, 30, 25, 24, 74.25, 1280 720 p 23.97, 59.94, 29.97 74.1758 smpte 296m 30, 25 74.25 1920 1080 i 29.97 74.1758 smpte 274m 30, 25, 24 74.25 1920 1080 p 23.98, 29.97, 74.1758 smpte 274m 1 other standards are support ed in async timing mode.
preliminary technical data ADV7322 rev. pra | page 5 of 88 clkin_a p_hsync p_vsync p_blank s_hsync s_vsync s_blank clkin_b hd pixel input sd pixel input luma and chroma filters y cb cr test pattern dnr gamma sync insertion ps 8 hdtv 2 rgb matrix sd 16 2 over- sampling dac dac dac dac dac dac f sc modu- lation cgms wss color control de- inter- leave y cb cr de- inter- leave test pattern y color cr color cb color timing generator timing generator clock control and pll 4:2:2 to 4:4:4 sharpness and adaptive filter control 05067-002 uv ssaf v u figure 2. detailed functional block diagram terminology sd: standard definition video, conforming to itu-r bt.601/itu-r bt.656. hd: high definition video, i.e., 720p/1080i/1035i. edtv: enhanced definition television (525p/625p) ps: progressive scan video, conforming to smpte 293m, itu-r bt.1358, btat-1004edtv2, or itu-r bt.13621362. hdtv: high definition television video, conforming to smpte 274m, or smpte 296m and smpte240m. ycrcb sd, ps, or hd component: digital video. yprpb sd, ps, or hd component: analog video.
ADV7322 preliminary technical data rev. pra | page 6 of 88 specifications v aa = 2.375 v ? 2.625 v, v dd = 2.375 v ? 2.625 v, v dd_io = 2.375 v ? 3.6 v, v ref = 1.235 v, r set = 3040 ?, r load = 300 ?. all specifications t min to t max (0c to 70c), unless otherwise noted. table 2. parameter min typ max unit test conditions static performance 1 resolution 11 bits integral nonlinearity 1.5 lsb differential nonlinearity 2 , +ve 0.5 lsb differential nonlinearity 2 , ?ve 1.0 lsb digital outputs output low voltage, v ol 0.4 [0.4] 3 v i sink = 3.2 ma output high voltage, v oh 2.4[2.0] 3 v i source = 400 a three-state leakage current 1.0 a v in = 0.4 v, 2.4 v three-state output capacitance 2 pf digital and control inputs input high voltage, v ih 2 v input low voltage, v il 0.8 v input leakage current 10 a v in = 2.4 v input capacitance, c in 2 pf analog outputs full-scale output current 4.1 4.33 4.6 ma output current range 4.1 4.33 4.6 ma dac to dac matching 1.0 % output compliance range, v oc 0 1.0 1.4 v output capacitance, c out 7 pf voltage reference internal reference range, v ref 1.15 1.235 1.3 v external reference range, v ref 1.15 1.235 1.3 v v ref current 4 10 a power requirements normal power mode i dd 5 137 ma sd only [16] 78 ma ps only [8] 73 ma hdtv only [2] 140 190 6 ma sd[16, 8 bit] + ps[8, 16 bit] i dd_io 1.0 ma i aa 7, 8 37 45 ma sleep mode i dd 80 a i aa 7 a i dd_io 250 a power supply rejection ratio 0.01 %/% 1 oversampling disabled. static dac performance will be improved with increased oversampling ratios. 2 dnl measures the deviation of the actual dac output voltage step from the ideal. for +ve dnl, the actual step value lies above the ideal step value; for ?ve dnl, the actual step value lies below the ideal step value. 3 value in brackets for v dd_io = 2.375 v ? 2.75 v. 4 external current required to overdrive internal v ref . 5 i dd , the circuit current, is the continuous current required to drive the digital core. 6 guaranteed maximum by characterization. 7 all dacs on. 8 i aa is the total current required to supply all dacs including the v ref circuitry and the pll circuitry.
preliminary technical data ADV7322 rev. pra | page 7 of 88 dynamic specifications v aa = 2.375 v ? 2.625 v, v dd = 2.375 v ? 2.625 v, v dd_io = 2.375 v ? 3.6 v, v ref = 1.235 v, r set = 3040 ?, r load = 300 ?. all specifications t min to t max (0c to 70c), unless otherwise noted. table 3. parameter min typ max unit test conditions progressive scan mode luma bandwidth 12.5 mhz chroma bandwidth 5.8 mhz snr 65.6 db luma ramp unweighted 72 db flat field full bandwidth hdtv mode luma bandwidth 30 mhz chroma bandwidth 13.75 mhz standard definition mode hue accuracy 0.4 degrees color saturation accuracy 0.4 % chroma nonlinear gain 1.2 % referenced to 40 ire chroma nonlinear phase ?0.2 degrees chroma/luma intermodulation 0 % chroma/luma gain inequality 97 % chroma/luma delay inequality ?1.1 ns luminance nonlinearity 0.5 % chroma am noise 84 db chroma pm noise 75.2 db differential gain 0.15 % ntsc differential phase 0.2 degrees ntsc snr 59.1 db luma ramp 77.1 db flat field full bandwidth
ADV7322 preliminary technical data rev. pra | page 8 of 88 timing specifications v aa = 2.375 v ? 2.625 v, v dd = 2.375 v ? 2.625 v, v dd_io = 2.375 v ? 3.6 v, v ref = 1.235 v, r set = 3040 ?, r load = 300 ?. all specifications t min to t max (0c to 70c), unless otherwise noted. table 4. parameter min typ max unit test conditions mpu port 1 sclock frequency 0 400 khz sclock high pulse width, t 1 0.6 s sclock low pulse width, t 2 1.3 s hold time (start condition), t 3 0.6 s first clock generated after this period relevant for repeated start condition setup time (start condition), t 4 0.6 s data setup time, t 5 100 ns sdata, sclock rise time, t 6 300 ns sdata, sclock fall time, t 7 300 ns setup time (stop condition), t 8 0.6 s reset low time 100 ns analog outputs analog output delay 2 7 ns output skew 1 ns clock control and pixel port 3 f clk 29.5 mhz sd pal square pixel mode f clk 81 mhz ps/hd async mode clock high time, t 9 40 % of one clk cycle clock low time, t 10 40 % of one clk cycle data setup time, t 11 1 2.0 ns data hold time, t 12 1 2.0 ns sd output access time, t 13 15 ns sd output hold time, t 14 5.0 ns hd output access time, t 13 14 ns hd output hold time, t 14 5.0 ns pipeline delay 4 63 clk cycles sd [2, 16] 76 clk cycles sd component mode [16] 35 clk cycles ps [1] 41 clk cycles ps [8] 36 clk cycles hd [2, 1] 1 guaranteed by characterization. 2 output delay measured from the 50% point of the rising edge of clock to the 50% point of dac output full-scale transition. 3 data: c[9:0]; y[9:0], s[9:0] control: p_hsync , p_vsync , p_blank , s_hsync , s_vsync , s_blank 4 sd, ps = 27 mhz, hd = 74.25 mhz.
preliminary technical data ADV7322 rev. pra | page 9 of 88 timing diagrams t 9 t 11 clkin_a c7?c0 t 10 t 12 control inputs y0 y1 y2 y3 y4 y5 y7?y0 t 14 control outputs t 13 t 9 = clock high time t 10 = clock low time t 11 = data setup time t 12 =dataholdtime p_hsync, p_vsync, p_blank cr4 cb4 cr2 cb2 cr0 cb0 05067-003 figure 3. hd only 4:2:2 input mode [input mode 010]; ps only 4:2:2 input mode [input mode 001] t 9 t 11 clkin_a c7?c0 t 10 t 12 control inputs y0 y1 y2 y3 y4 y5 y7?y0 t 14 control outputs t 13 t 9 =clockhightime t 10 = clock low time t 11 = data setup time t 12 = data hold time s7?s0 cr4 cr3 cr2 cr1 cr0 cr5 cb4 cb3 cb2 cb1 cb0 cb5 p_hsyn c, p_vsync, p_blank 05067-004 figure 4. hd only 4:4:4 input mode [input mode 010]; ps only 4:4:4 input mode [input mode 001]
ADV7322 preliminary technical data rev. pra | page 10 of 88 t 9 t 11 clkin_a c7?c0 t 10 t 12 p_hsync, p_vsync, p_blank control inputs g0 g1 g2 g3 g4 g5 b0 b1 b2 b3 b4 b5 r0 r1 r2 r3 r4 r5 y7?y0 t 14 control outputs t 13 t 9 = clock high time t 10 = clock low time t 11 = data setup time t 12 =dataholdtime s7?s0 05067-005 figure 5. hd rgb 4:4:4 input mode [input mode 010] t 9 t 11 t 10 t 12 t 11 t 12 t 13 t 14 clkin_b* *clkin_b must be used in this ps mode. y7?y0 t 9 = clock high time t 10 = clock low time t 11 = data setup time t 12 =dataholdtime control inputs control outputs yxxx crxxx y1 cr0 y0 cb0 p_hsync, p_vsync, p_blank 05067-006 figure 6. ps 4:2:2 8-bit interleaved at 27 mhz hsync / vsync input mode [input mode 100]
preliminary technical data ADV7322 rev. pra | page 11 of 88 t 9 t 11 t 10 t 12 t 14 t 13 clkin_a y7?y0 t 9 = clock high time t 10 = clock low time t 11 = data setup time t 12 =dataholdtime control inputs control outputs yxxx crxxx y1 cr0 y0 cb0 p_vsync, p_hsync, p_blank 05067-007 figure 7. ps 4:2:2 8-bit interleaved at 54 mhz hsync / vsync input mode [input mode 111] t 9 t 11 t 10 t 12 t 11 t 12 t 13 t 14 clkin_b* *clkin_b used in this ps only mode. y7?y0 t 9 =clockhightime t 10 = clock low time t 11 = data setup time t 12 =dataholdtime control outputs y1 cr0 y0 cb0 xy 00 00 ff 05067-008 figure 8. ps only 4:2:2 8-bit interleaved at 27 mhz eav/sav input mode [input mode 100]
ADV7322 preliminary technical data rev. pra | page 12 of 88 t 9 t 11 t 10 t 12 t 14 t 13 clkin_a y7?y0 t 9 = clock high time t 10 = clock low time t 11 = data setup time t 12 =dataholdtime control outputs note: y0, cb0 sequence as per subaddress 0x01 bit-1 ff 00 00 xy cb0 y0 cr0 y1 05067-009 figure 9. ps only 4:2:2 8-bit interleaved at 54 mhz eav/sav input mode [input mode 111] t 9 t 11 t 10 t 12 y0 y1 y2 y3 y4 y5 t 9 t 10 t 11 t 12 hd input sd input s7?s0 control inputs clkin_a clkin_b y7?y0 control inputs c7?c0 p_hsync, p_vsync, p_blank y2 cb1 y1 cr0 y0 cb0 s_hsync, s_vsync, s_blank cr4 cb4 cr2 cb2 cr0 cb0 05067-010 figure 10. hd 4:2:2 and sd (8-bit) simultaneous input mode [input mode 101: sd oversampled] [input mode 110: hd oversampled]
preliminary technical data ADV7322 rev. pra | page 13 of 88 t 9 t 11 t 10 t 12 y0 y1 y2 y3 y4 y5 t 9 t 10 t 11 t 12 ps input sd input s7?s0 control inputs clkin_a clkin_b y7?y0 control inputs c7?c0 p_hsync, p_vsync, p_blank y2 cb1 y1 cr0 y0 cb0 s_hsync, s_vsync, s_blank cr4 cb4 cr2 cb2 cr0 cb0 05067-011 figure 11. ps (4:2:2) and sd (8-bit) simu ltaneous input mode [input mode 011] t 9 t 11 t 10 t 12 t 11 t 12 clkin_b y7?y0 control inputs yxxx crxxx y1 cr0 y0 cb0 p_hsync, p_vsync, p_blank ps input t 9 t 10 t 11 t 12 sd input s7?s0 control inputs clkin_a y2 cb1 y1 cr0 y0 cb0 s_hsync, s_vsync, s_blank 05067-012 figure 12. ps (8-bit) and sd (8-bit) simu ltaneous input mode [input mode 100]
ADV7322 preliminary technical data rev. pra | page 14 of 88 t 9 t 11 clkin_a t 10 t 12 control inputs t 14 control outputs t 13 s_hsync, s_vsync, s_blank cr4 cb4 cr2 cb2 cr0 cb0 05067-013 s7?s0/y7?y0* *selected by address 0x01 bit 7 in master/slave mode in slave mode figure 13. 8-bit sd only pixel input mode [input mode 000] t 9 t 11 clkin_a c7?c0* t 10 t 12 cb0 cr0 cb2 cr2 control inputs t 14 control outputs t 13 *selected by address 0x01 bit 7: see table 21. in master/slave mode in slave mode s7?s0/y7?y0* y0 y2 y3 y1 s_hsync, s_vsync, s_blank 05067-014 figure 14. 16-bit sd only pixel input mode [input mode 000]
preliminary technical data ADV7322 rev. pra | page 15 of 88 y7?y0 y0 y1 y2 y3 b a a and b as per relevant standard c7?c0 cb1 cr1 cr0 cb0 p_hsync p_vsync p_blank 05067-015 figure 15. hd 4:2:2 input timing diagram y7?y0 cb y cr y b a a=32clkcyclesfor525p a=24clkcyclesfor625p as recommended by standard b(min) = 244 clkcycles for 525p b(min) = 264 clkcycles for 625p p_hsync p_vsync p_blank 05067-016 figure 16. ps 4:2:2 8-bit interleaved input timing diagram
ADV7322 preliminary technical data rev. pra | page 16 of 88 cb y cr y pal = 24 clk cycles ntsc = 32 clk cycles pal = 24 clk cycles ntsc = 32 clk cycles s7?s0/y7?y0* *selected by address 0x01 bit 7 s_hsync s_vsync s_blank 05067-017 figure 17. sd timing input for timing mode 1 t 3 t 1 t 6 t 2 t 7 t 5 sda sclk t 3 t 4 t 8 05067-018 figure 18. mpu port timing diagram
preliminary technical data ADV7322 rev. pra | page 17 of 88 absolute maximum ratings table 5. parameter 1 value v aa to agnd ?0.3 v to +3.0 v v dd to dgnd ?0.3 v to +3.0 v v dd_io to gnd_io ?0.3 v to 4.6 v digital input voltage to dgnd ?0.3 v to v dd_io +0.3 v v aa to v dd ?0.3 v to +0.3 v agnd to dgnd ?0.3 v to +0.3 v dgnd to gnd_io ?0.3 v to +0.3 v agnd to gnd_io ?0.3 v to +0.3 v ambient operating temperature (t a ) 0c to 70c storage temperature (t s ) C65c to +150c infrared reflow soldering (20 s) 260c 1 analog output short circuit to any power supply or common can be of an indefinite duration. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics jc = 11c/w ja = 47c/w the ADV7322 is a pb-free environmentally friendly product. it is manufactured using the most up-to-date materials and processes. the coating on the leads of each device is 100% pure sn electroplate. the device is suitable for pb-free applications and is able to withstand surface-mount soldering at up to 255c (5c). in addition, it is backward-compatible with conventional snpb soldering processes. this means that the electroplated sn coating can be soldered with sn/pb solder pastes at conventional reflow temperatures of 220c to 235c. esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discha rges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ADV7322 preliminary technical data rev. pra | page 18 of 88 pin configuration and fu nction descriptions 64 gnd_io 63 clkin_b 62 s7 61 s6 60 s5 59 s4 58 s3 57 dgnd 56 v dd 55 s2 54 s1 53 s0 52 test5 51 test4 50 s_hsync 49 s_vsync 47 r set1 46 v ref 45 comp1 42 dac c 43 dac b 44 dac a 48 s_blank 41 v aa 40 agnd 39 dac d 37 dac f 36 comp2 35 r set2 34 ext_lf 33 reset 38 dac e 2 test0 3 test1 4 y0 7 y3 6 y2 5 y1 1 v dd_io 8 y4 9 y5 10 v dd 12 y6 13 y7 14 test2 15 test3 16 c0 11 dgnd 17 c1 18 c2 19 i 2 c 20 alsb 21 sda 22 sclk 23 p_hsync 24 p_vsync 25 p_blank 26 c3 27 c4 28 c5 29 c6 30 c7 31 rtc_scr_tr 32 clkin_a pin 1 ADV7322 top view (not to scale) 05067-019 figure 19. pin configuration
preliminary technical data ADV7322 rev. pra | page 19 of 88 table 6. pin function descriptions mnemonic input/output function dgnd g digital ground. agnd g analog ground. clkin_a i pixel clock input for hd (74.25 mhz only, ps only (27 mhz), sd only (27 mhz). clkin_b i pixel clock input. requires a 27 mhz reference cloc k for progressive scan mode or a 74.25 mhz (74.1758 mhz) reference clock in hdtv mode. this clock is only used in dual modes. comp1, comp2 o compensation pin for dacs. connect 0.1 f capacitor from comp pin to v aa . dac a o cvbs/green/y/y analog output. dac b o chroma/blue/u/pb analog output. dac c o luma/red/v/pr analog output. dac d o in sd only mode: cvbs/green/y analog output; in hd only mode and simultaneous hd/sd mode: y/green [hd] analog output. dac e o in sd only mode: luma/blue/u anal og output; in hd only mode and simultaneous hd/sd mode: pr/red analog output. dac f o in sd only mode: chroma/red/v analog output; in hd only mode and simultaneous hd/sd mode: pb/blue [hd] analog output. p_hsync i video horizontal sync control signal for hd in simultaneous sd/hd mode and hd only mode. p_vsync i video vertical sync control signal for hd in simultaneous sd/hd mode and hd only mode. p_blank i video blanking control signal for hd in simultaneous sd/hd mode and hd only mode. s_blank i/o video blanking control signal for sd only. s_hsync i/o video horizontal sync control signal for sd only. s_vsync i/o video vertical sync control signal for sd only. y7 to y0 i sd or progressive scan/hdtv input port for y data. input port for interleaved pr ogressive scan data. the lsb is set up on pin y0. c7 to c0 i progressive scan/hdtv input port 4:4:4 input mode. this port is used for the cb [blu e/u] data. the lsb is set up on pin c0. s7 to s0 i sd or progressive scan/hdtv input port for cr [red/v] data in 4:4:4 input mode. lsb is set up on pin s0. reset i this input resets the on-chip ti ming generator and sets the adv 7322 into default register setting. reset is an active low signal. r set1 , r set2 i a 3040 ? resistor must be connected from this pin to agnd and is used to control the amplitudes of the dac outputs. sclk i i 2 c port serial interface clock input. sda i/o i 2 c port serial data input/output. alsb i ttl address input. this signal sets up the lsb of the i 2 c address. when this pin is tied low, the i 2 c filter is activated, which reduces noise on the i 2 c interface. v dd_io p power supply for digi tal inputs and outputs. v dd p digital power supply. v aa p analog power supply. v ref i/o optional external voltage reference input for dacs or voltage reference output (1.235 v). ext_lf i external loop fi lter for the internal pll. rtc_scr_tr i multifunctional input. real time control (r tc) input, timing reset input, subcarrier reset input. i 2 c i this input pin must be tied high (v dd_io ) for the ADV7322 to interface over the i 2 c port. gnd_io digital input/output ground. test0 to test5 i not used. tie to dgnd
ADV7322 preliminary technical data rev. pra | page 20 of 88 typical performance characteristics frequency (mhz) prog scan pr/pb response. linear interp from 4:2:2 to 4:4:4 0 gain (db) ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?80 200 20 40 60 80 100 120 140 160 180 0 05067-045 figure 20. psuv 8 oversampling filter (linear) frequency (mhz) prog scan pr/pb response. ssaf interp from 4:2:2 to 4:4:4 0 gain (db) ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?80 200 20 40 60 80 100 120 140 160 180 0 05067-046 figure 21. psuv 8 oversampling filter (ssaf) frequency (mhz) y response in ps o v ers a mpling mode 0 gain (db) ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?80 200 20 40 60 80 100 120 140 160 180 0 05067-047 figure 22. psy (8 oversampling filter) frequency (mhz) yp a ss b a nd in ps o v ers a mpling mode gain (db) ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 ?3.0 12 246810 0 05067-048 figure 23. psy 8 oversampling filter (pass band) frequency (mhz) pr / pb response in hdt v o v ers a mpling mode 0 gain (db) ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?80 140 20 40 60 80 100 120 0 05067-049 figure 24. hdtvuv (2 oversampling filter) frequency (mhz) y response in hdtv oversampling mode 0 gain (db) ?70 ?60 ?50 ?40 ?30 ?20 ?10 ?80 140 20 40 60 80 100 120 0 05067-050 figure 25. hdtvy (2 oversampling filter)
preliminary technical data ADV7322 rev. pra | page 21 of 88 frequency (mhz) magnitude (db) 0 12 10 8 6 4 2 0 ?10 ?30 ?50 ?60 ?70 ?20 ?40 05067-051 figure 26. luma ntsc low-pass filter frequency (mhz) magnitude (db) 0 12 10 8 6 4 2 0 ?10 ?30 ?50 ?60 ?70 ?20 ?40 05067-052 figure 27. luma pal low-pass filter frequency (mhz) magnitude (db) 0 12 10 8 6 4 2 0 ?10 ?30 ?50 ?60 ?70 ?20 ?40 05067-053 figure 28. luma ntsc notch filter frequency (mhz) magnitude (db) 0 12 10 8 6 4 2 0 ?10 ?30 ?50 ?60 ?70 ?20 ?40 05067-054 figure 29. luma pal notch filter frequency (mhz) y response in sd oversampling mode gain (db) 0 ?50 ?80 0 20 40 60 80 100 120 140 160 180 200 ?10 ?40 ?60 ?70 ?20 ?30 05067-055 figure 30. y16 oversampling filter frequency (mhz) magnitude (db) 0 12 10 8 6 4 2 0 ?10 ?30 ?50 ?60 ?70 ?20 ?40 05067-056 figure 31. luma ssaf filter up to 12 mhz
ADV7322 preliminary technical data rev. pra | page 22 of 88 frequency (mhz) 4 7 magnitude (db) 2 ?2 ?6 ?8 ?12 0 ?4 5 ?10 6 05067-057 0 1 234 figure 32. luma ssaf filterprogrammable responses frequency (mhz) 7 magnitude (db) 5 4 2 1 ?1 3 5 0 6 05067-058 0 1 234 figure 33. luma ssaf filterprogrammable gain frequency (mhz) 7 magnitude (db) 1 0 ?2 ?3 ?5 ?1 5 ?4 6 05067-059 0 1 23 4 figure 34. luma ssaf filterprogrammable attenuation frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 05067-060 8 4 6 2 0 figure 35. luma cif low-pass filter frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 8 4 6 2 0 05067-061 figure 36. luma qcif low-pass filter frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 8 4 6 2 0 05067-062 figure 37. chroma 3.0 mhz low-pass filter
preliminary technical data ADV7322 rev. pra | page 23 of 88 frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 8 4 6 2 0 05067-063 figure 38. chroma 2.0 mhz low-pass filter frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 8 4 6 2 0 05067-064 figure 39. chroma 1.3 mhz low-pass filter frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 8 4 6 2 0 05067-065 figure 40. chroma 1.0 mhz low-pass filter frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 8 4 6 2 0 05067-066 figure 41. chroma 0.65 mhz low-pass filter frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 8 4 6 2 0 05067-067 figure 42. chroma cif low-pass filter frequency (mhz) 0 12 magnitude (db) ?10 ?30 ?50 ?60 ?70 ?20 ?40 10 8 4 6 2 0 05067-068 figure 43. chroma qcif low-pass filter
ADV7322 preliminary technical data rev. pra | page 24 of 88 mpu port description the ADV7322 supports a 2-wire serial (i 2 c-compatible) microprocessor bus driving multiple peripherals. this port operates in an open-drain configuration. two inputs, serial data (sda) and serial clock (scl), carry information between any device connected to the bus and the ADV7322. each slave device is recognized by a unique address. the ADV7322 has four possible slave addresses for both read and write operations. these are unique addresses for each device and are illustrated in figure 44. the lsb sets either a read or write operation. logic 1 corresponds to a read operation, while logic 0 corresponds to a write operation. a1 is set by setting the alsb pin of the ADV7322 to logic 0 or logic 1. when alsb is set to 1, there is greater input bandwidth on the i 2 c lines, which allows high speed data transfers on this bus. when alsb is set to 0, there is reduced input bandwidth on the i 2 c lines, which means that pulses of less than 50 ns will not pass into the i 2 c internal controller. this mode is recommended for noisy systems. 1 1 0 1 0 1 a1 x address control set up by alsb read/write control 0 write 1 read 05067-020 figure 44. ADV7322 slave address = 0xd4 to control the various devices on the bus, the following protocol must be followed. first the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on sda while scl remains high. this indicates that an address/data stream will follow. all peripherals respond to the start condition and shift the next eight bits (7-bit address + r/ w bit). the bits are transferred from msb down to lsb. the peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as an acknowledge bit. all other devices withdraw from the bus at this point and maintain an idle condition. the idle condition is where the device monitors the sda and scl lines waiting for the start condition and the correct transmitted address. the r/ w bit determines the direction of the data. logic 0 on the lsb of the first byte means that the master will write information to the peripheral. logic 1 on the lsb of the first byte means that the master will read information from the peripheral. the ADV7322 acts as a standard slave device on the bus. the data on the sda pin is eight bits long, supporting the 7-bit addresses plus the r/ w bit. it interprets the first byte as the device address and the second byte as the starting subaddress. there is a subaddress auto-increment facility. this allows data to be written to or read from registers in ascending subaddress sequence starting at any valid subaddress. a data transfer is always terminated by a stop condition. the user can also access any unique subaddress register on a one-by-one basis without having to update all the registers. stop and start conditions can be detected at any stage during the data transfer. if these conditions are asserted out of sequence with normal read and write operations, then they cause an immediate jump to the idle condition. during a given scl high period, the user should only issue one start condition, one stop condition, or a single stop condition followed by a single start condition. if an invalid subaddress is issued by the user, the ADV7322 will not issue an acknowledge and will return to the idle condition. if in auto-increment mode the user exceeds the highest subaddress, the following action is taken: 1. in read mode, the highest subaddress register contents are output until the master device issues a no-acknowledge. this indicates the end of a read. a no-acknowledge condition is when the sda line is not pulled low on the ninth pulse. 2. in write mode, the data for the invalid byte is not loaded into any subaddress register, a no-acknowledge is issued by the ADV7322, and the part returns to the idle condition. before writing to the subcarrier frequency registers, it is a requirement that the ADV7322 is reset at least once after power-up. the four subcarrier frequency registers must be updated, starting with subcarrier frequency register 0 through subcarrier frequency register 3. the subcarrier frequency will not update until the last subcarrier frequency register byte has been received by the ADV7322. figure 45 illustrates an example of data transfer for a write sequence and the start and stop conditions. figure 46 shows bus write and read sequences.
preliminary technical data ADV7322 rev. pra | page 25 of 88 sdata sclock start adrr r/w ack subaddress ack data ack stop 1?7 8 9 s 1?7 1?7 p 05067-022 8 9 8 9 figure 45. bus data transfer write sequence read sequence s slave addr a(s) subaddr a(s) data data a(s) p s slave addr a(s) subaddr a(s) s slave addr a(s) data data a(m) a(m) p s = start bit p = stop bit a(s) = acknowledge by slave a(m) = acknowledge by master a (s) = no-acknowledge by slave a (m) = no-acknowledge by master lsb = 0 lsb = 1 05067-023 a(s) figure 46. read and write sequence
ADV7322 preliminary technical data rev. pra | page 26 of 88 register access the mpu can write to or read from all of the registers of the ADV7322 except the subaddress registers, which are write only registers. the subaddress register determines which register the next read or write operation will access. all communications with the part through the bus start with an access to the subaddress register. a read/write operation is then performed from/to the target address, which increments to the next address until a stop command is performed on the bus. register programming the following tables describe the functionality of each register. all registers can be read from as well as written to, unless otherwise stated. subaddress register (sr7 to sr0) the communication register is an 8-bit write-only register. after the part is accessed over the bus and a read/write operation is selected, the subaddress is set up. the subaddress register determines to/from which register the operation takes place. table 7. registers 0x00 to 0x01 sr7C sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reg. reset values (shaded) 0 sleep mode off. 0xfc sleep mode. with this control enabled, the current consumption is reduced to a level. all dacs and the internal pll cct are disabled. i 2 c registers can be read from and written to in sleep mode. 1 sleep mode on. 0 pll on. pll and oversampling control. this control allows the internal pll cct to be powered down and the oversampling to be switched off. 1 pll off. 0 dac f off. dac f: power on/off. 1 dac f on. 0 dac e off. dac e: power on/off. 1 dac e on. 0 dac d off. dac d: power on/off. 1 dac d on. 0 dac d off. dac c: power on/off. 1 dac c on. 0 dac b off. dac b: power on/off. 1 dac b on. 0 dac a off. 0x00 power mode register dac a: power on/off. 1 dac a on. reserved 0 reserved 0 cb clocked on rising edge. clock edge. 1 y clocked on rising edge only for ps interleaved input at 27 mhz. reserved. 0 0 clock align. 1 must be set if the phase delay between the two input clocks is <9.25 ns or >27.75 ns. only if two input clocks are used. 0 0 0 sd input only. 0x38 0 0 1 ps input only. 0 1 0 hdtv input only. 0 1 1 sd and ps [16-bit]. 1 0 0 sd and ps [8-bit]. 1 0 1 sd and hdtv [sd oversampled]. 1 1 0 sd and hdtv [hdtv oversampled]. input mode. 1 1 1 ps only [at 54 mhz]. 0 0x01 mode select register y/c/s bus swap. 1 allows data to be applied to data ports in various configurations (sd feature only). see table 21.
preliminary technical data ADV7322 rev. pra | page 27 of 88 table 8. registers 0x02 to 0x0f sr7C sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset values reserved 0 0 zero must be written to these bits. 0x20 0 disabled. test pattern black bar 1 enabled. 0x11, bit 2 must also be enabled. 0 disable manual rgb matrix adjust. manual rgb matrix adjust 1 enable manual rgb matrix adjust. 0 no sync. sync on rgb 1 1 sync on all rgb outputs. 0 rgb component outputs. rgb/yprpb output 1 yprpb component outputs. 0 no sync output. sd sync 1 output sd syncs on s_hsync , s_vsync , s_blank pins. 0 no sync output. 0x02 mode register 0 hd sync 1 output hd,ed, syncs on s_hsync , s_vsync . 0x03 rgb matrix 0 x x lsb for gy. 0x03 x x lsb for rv. 0xf0 x x lsb for bu. x x lsb for gv. 0x04 rgb matrix 1 x x lsb for gu. 0x05 rgb matrix 2 x x x x x x x x bits 9C2 for gy. 0x4e 0x06 rgb matrix 3 x x x x x x x x bits 9C2 for gu. 0x0e 0x07 rgb matrix 4 x x x x x x x x bits 9C2 for gv. 0x24 0x08 rgb matrix 5 x x x x x x x x bits 9C2 for bu. 0x92 0x09 rgb matrix 6 x x x x x x x x bits 9C2 for rv. 0x7c 0x0a dac a, b, c output level 2 positive gain to dac output voltage 0 0 0 0 0 0 0 0 0% 0x00 0 0 0 0 0 0 0 1 +0.018% 0 0 0 0 0 0 1 0 0.036% 0 0 1 1 1 1 1 1 +7.382% 0 1 0 0 0 0 0 0 +7.5% negative gain to dac output voltage 1 1 0 0 0 0 0 0 ?7.5% 1 1 0 0 0 0 0 1 ?7.382% 1 0 0 0 0 0 1 0 ?7.364% 1 1 1 1 1 1 1 1 ?0.018% 0x0b dac d, e, f output level positive gain to dac output voltage 0 0 0 0 0 0 0 0 0% 0x00 0 0 0 0 0 0 0 1 +0.018% 0 0 0 0 0 0 1 0 0.036% 0 0 1 1 1 1 1 1 +7.382% 0 1 0 0 0 0 0 0 +7.5% negative gain to dac output voltage 1 1 0 0 0 0 0 0 ?7.5% 1 1 0 0 0 0 0 1 ?7.382% 1 0 0 0 0 0 1 0 ?7.364% 1 1 1 1 1 1 1 1 ?0.018% 0x0c reserved 0x00 0x0d reserved 0x00 0x0e reserved 0x00 0x0f reserved 0x00 1 for more detail, refe r to appendix 7. 2 for more detail on the pr ogrammable output levels, refer to the programmable dac gain control section.
ADV7322 preliminary technical data rev. pra | page 28 of 88 table 9. registers 0x10 to 0x11 sr7C sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting note reset values 0 0 eia770.2 output 0x00 0 1 eia770.1 output 1 0 output levels for full input range hd output standard 1 1 reserved 0 hsync , vsync , blank input sync format 1 eav/sav codes 0 0 0 0 0 smpte 293m, itu- bt 1358 525p @ 59.94 hz 0 0 0 0 1 async mode 0 0 0 1 0 bta-1004, itu- bt 1362 525p @ 59.94 hz 0 0 0 1 1 itu-bt 1358 625p @ 50 hz 0 0 1 0 0 itu-bt 1362 625p @ 50 hz 0 0 1 0 1 smpte 296m-1, 2 720p @ 60/59.94 hz 0 0 1 1 0 smpte 296m-3 720p @ 50 hz 0 0 1 1 1 smpte 296m-4, 5 720p @ 30/29.97 hz 0 1 0 0 0 smpte 296m-6 720p @ 25 hz 0 1 0 0 1 smpte 296m-7, 8 720p @ 24/23.98 hz 0 1 0 1 0 smpte 240m 1035i @ 60/59.94 hz 0 1 0 1 1 reserved 0 1 1 0 0 reserved 0 1 1 0 1 smpte 274m-4,5 1080i @ 30/29.97 hz 0 1 1 1 0 smpte 274m-6 1080i @ 25 hz 0 1 1 1 1 smpte 274m-7, 8 1080p @ 30/29.97 hz 1 0 0 0 0 smpte 274m-9 1080p @ 25 hz 1 0 0 0 1 smpte 274m- 10, 11 1080p @ 24/23.98 hz 0x10 hd mode register 1 hd/ed input mode 10010C11111 reserved 0 pixel data valid off 1 pixel data valid on 0x00 hd pixel data valid 0 reserved 0 hd test pattern off hd test pattern enable 1 hd test pattern on 0 hatch hd test pattern hatch/field 1 field/frame 0 disabled hd vbi open 1 enabled 0 0 disabled 0 1 ?11 ire 1 0 ?6 ire hd undershoot limiter 1 1 ?1.5 ire only available in edtv (525p/625p) 0 disabled 0x11 hd mode register 2 hd sharpness filter 1 enabled
preliminary technical data ADV7322 rev. pra | page 29 of 88 table 10. register 0x12 sr7C sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset values 0 0 0 0 clk cycles 0x00 0 0 1 1 clk cycles 0 1 0 2 clk cycles 0 1 1 3 clk cycles hd y delay with respect to falling edge of hsync 1 0 0 4 clk cycles 0 0 0 0 clk cycles 0 0 1 1 clk cycle 0 1 0 2 clk cycles 0 1 1 3 clk cycles hd color delay with respect to falling edge of hsync 1 0 0 4 clk cycles 0 disabled hd cgms 1 enabled 0 disabled 0x12 hd mode register 3 hd cgms crc 1 enabled table 11. registers 0x13 to 0x14 sr7C sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset values 0 cb after falling edge of hsync . 0x4c hd cr/cb sequence 1 cr after falling edge of hsync . reserved 0 0 must be written to this bit. reserved 0 0 must be written here 0 disabled. sinc filter on dac d, e, f 1 enabled. reserved 0 0 must be written to this bit. 0 disabled. hd chroma ssaf 1 enabled. 0 4:4:4 hd chroma input 1 4:2:2 0 disabled. 0x13 hd mode register 4 hd double buffering 1 enabled. hd timing reset x a low-high-low transition resets the internal hd timing counters. 0x00 0 signal duration on s_hsync same as adv731x. hd hsync generation 1 1 signal duration on s_hsync = sync duration on embedded y. 0 field signal out on s_vsync pin. hd vsync generation 1 1 vsync signal. d uration = vsync on embedded y. 0 blank active high. hd blank polarity 1 blank active low. 0 macrovision disabled. hd macrovision for 525p and 625p 1 macrovision enabled. reserved 0 0 must be written to these bits. 0 0 = field input. hd vsync /field input 1 1 = vsync input. 0 update horizontal/vertical counters. 0x14 hd mode register 5 horizontal/vertical counters 2 1 horizontal/vertical counters free running. 1 used in conjunction with hd_sync in register 0x02, bit 7 set to 1. 2 when set to 0, the horizontal/vertical counters automatically wr ap around at the end of the line/field/frame of the standard s elected. when set to 1, the horizontal/vertical counters are free running and wrap around when external sync signals indicate so.
ADV7322 preliminary technical data rev. pra | page 30 of 88 table 12. register 0x15 sr7C sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset values reserved 0 0 must be written to this bit 0x00 0 disabled hd rgb input 1 enabled 0 disabled hd sync on prpb 1 enabled 0 dac e = pb; dac f = pr hd color dac swap 1 dac e = pr; dac f = pb 0 gamma curve a hd gamma curve a/b 1 gamma curve b 0 disabled hd gamma curve enable 1 enabled 0 mode a hd adaptive filter mode 1 mode b 0 disabled 0x15 hd mode register 6 hd adaptive filter enable 1 enabled
preliminary technical data ADV7322 rev. pra | page 31 of 88 table 13. registers 0x16 to 0x37 sr7C sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset values 0x16 hd y level 1 x x x x x x x x y level value 0xa0 0x17 hd cr level 1 x x x x x x x x cr level value 0x80 0x18 hd cb level 1 x x x x x x x x cb level value 0x80 0x19 reserved 0x00 0x1a reserved 0x00 0x1b reserved 0x00 0x1c reserved 0x00 0x1d reserved 0x00 0x1e reserved 0x00 0x1f reserved 0x00 0 0 0 0 gain a = 0 0x00 0 0 0 1 gain a = +1 0 1 1 1 gain a = +7 1 0 0 0 gain a = ?8 hd sharpness filter gain value a 1 1 1 1 gain a = ?1 0 0 0 0 gain b = 0 0 0 0 1 gain b = +1 0 1 1 1 gain b = +7 1 0 0 0 gain b = ?8 0x20 hd sharpness filter gain hd sharpness filter gain value b 1 1 1 1 gain b = ?1 0x21 hd cgms data 0 hd cgms data bits 0 0 0 0 c19 c18 c 17 c16 cgms 19C16 0x00 0x22 hd cgms data 1 hd cgms data bits c15 c 14 c13 c12 c11 c10 c9 c8 cgms 15C8 0x00 0x23 hd cgms data 2 hd cgms data bits c7 c6 c5 c4 c3 c2 c1 c0 cgms 7C0 0x00 0x24 hd gamma a hd gamma curve a data points x x x x x x x x a0 0x00 0x25 hd gamma a hd gamma curve a data points x x x x x x x x a1 0x00 0x26 hd gamma a hd gamma curve a data points x x x x x x x x a2 0x00 0x27 hd gamma a hd gamma curve a data points x x x x x x x x a3 0x00 0x28 hd gamma a hd gamma curve a data points x x x x x x x x a4 0x00 0x29 hd gamma a hd gamma curve a data points x x x x x x x x a5 0x00 0x2a hd gamma a hd gamma curve a data points x x x x x x x x a6 0x00 0x2b hd gamma a hd gamma curve a data points x x x x x x x x a7 0x00 0x2c hd gamma a hd gamma curve a data points x x x x x x x x a8 0x00 0x2d hd gamma a hd gamma curve a data points x x x x x x x x a9 0x00 0x2e hd gamma b hd gamma curve b data points x x x x x x x x b0 0x00 0x2f hd gamma b hd gamma curve b data points x x x x x x x x b1 0x00 0x30 hd gamma b hd gamma curve b data points x x x x x x x x b2 0x00 0x31 hd gamma b hd gamma curve b data points x x x x x x x x b3 0x00 0x32 hd gamma b hd gamma curve b data points x x x x x x x x b4 0x00 0x33 hd gamma b hd gamma curve b data points x x x x x x x x b5 0x00 0x34 hd gamma b hd gamma curve b data points x x x x x x x x b6 0x00 0x35 hd gamma b hd gamma curve b data points x x x x x x x x b7 0x00 0x36 hd gamma b hd gamma curve b data points x x x x x x x x b8 0x00 0x37 hd gamma b hd gamma curve b data points x x x x x x x x b9 0x00 1 for use with internal test pattern only.
ADV7322 preliminary technical data rev. pra | page 32 of 88 table 14. registers 0x38 to 0x3d sr7C sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset values 0 0 0 0 gain a = 0 0x00 0 0 0 1 gain a = +1 0 1 1 1 gain a = +7 1 0 0 0 gain a = ?8 hd adaptive filter gain 1 value a 1 1 1 1 gain a = ?1 0 0 0 0 gain b = 0 0 0 0 1 gain b = +1 0 1 1 1 gain b = +7 1 0 0 0 gain b = ?8 0x38 hd adaptive filter gain 1 hd adaptive filter gain 1 value b 1 1 1 1 gain b = ?1 0 0 0 0 gain a = 0 0x00 0 0 0 1 gain a = +1 0 1 1 1 gain a = +7 1 0 0 0 gain a = ?8 hd adaptive filter gain 2 value a 1 1 1 1 gain a = ?1 0 0 0 0 gain b = 0 0 0 0 1 gain b = +1 0 1 1 1 gain b = +7 1 0 0 0 gain b = ?8 0x39 hd adaptive filter gain 2 hd adaptive filter gain 2 value b 1 1 1 1 gain b = ?1 0 0 0 0 gain a = 0 0x00 0 0 0 1 gain a = +1 0 1 1 1 gain a = +7 1 0 0 0 gain a = ?8 hd adaptive filter gain 3 value a 1 1 1 1 gain a = ?1 0 0 0 0 gain b = 0 0 0 0 1 gain b = +1 0 1 1 1 gain b = +7 1 0 0 0 gain b = ?8 0x3a hd adaptive filter gain 3 hd adaptive filter gain 3 value b 1 1 1 1 gain b = ?1 0x3b hd adaptive filter threshold a hd adaptive filter threshold a value x x x x x x x x threshold a 0x00 0x3c hd adaptive filter threshold b hd adaptive filter threshold b value x x x x x x x x threshold b 0x00 0x3d hd adaptive filter threshold c hd adaptive filter threshold c value x x x x x x x x threshold c 0x00
preliminary technical data ADV7322 rev. pra | page 33 of 88 table 15. registers 0x3e to 0x43 sr7C sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset values 0x3e reserved 0x00 0x3f reserved 0x00 0 0 ntsc 0x00 0 1 pal b, d, g, h, i 1 0 pal m sd standard 1 1 pal n 0 0 0 lpf ntsc 0 0 1 lpf pal 0 1 0 notch ntsc 0 1 1 notch pal 1 0 0 ssaf luma 1 0 1 luma cif 1 1 0 luma qcif sd luma filter 1 1 1 reserved 0 0 0 1.3 mhz 0 0 1 0.65 mhz 0 1 0 1.0 mhz 0 1 1 2.0 mhz 1 0 0 reserved 1 0 1 chroma cif 1 1 0 chroma qcif 0x40 sd mode register 0 sd chroma filter 1 1 1 3.0 mhz 0x41 reserved 0x00 0 disabled sd prpb ssaf 1 enabled 0x08 0 sd dac output 1 1 refer to output configuration section 0 sd dac output 2 1 refer to output configuration section 0 disabled sd pedestal 1 enabled 0 disabled sd square pixel 1 enabled 0 disabled sd vcr ff/rw sync 1 enabled 0 disabled sd pixel data valid 1 enabled 0 disabled 0x42 sd mode register 1 sd sav/eav step edge control 1 enabled 0 no pedestal on yuv sd pedestal yprpb output 1 7.5 ire pedestal on yuv 0x00 0 y = 700 mv/300 mv sd output levels y 1 y = 714 mv/286 mv 0 0 700 mv p-p[pal]; 1000 mv p-p[ntsc] 0 1 700 mv p-p 1 0 1000 mv p-p sd output levels prpb 1 1 648 mv p-p 0 disabled sd vbi open 1 enabled 0 0 cc disabled 0 1 cc on odd field only 1 0 cc on even field only sd cc field control 1 1 cc on both fields 0x43 sd mode register 2 reserved 0 reserved
ADV7322 preliminary technical data rev. pra | page 34 of 88 table 16. registers 0x44 to 0x49 sr7C sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset values 0 disabled sd vsync-3h 1 vsync = 2.5 lines [pal], vsync = 3 lines [ntsc] 0x00 0 0 genlock disabled 0 1 subcarrier reset 1 0 timing reset sd rtc/tr/scr 1 1 rtc enabled 0 720 pixels sd active video length 1 710 [ntsc]/702[pal] 0 chroma enabled sd chroma 1 chroma disabled 0 enabled sd burst 1 disabled 0 disabled sd color bars 1 enabled 0 dac a = luma, dac b = chroma 0x44 sd mode register 3 sd dac swap 1 dac a = chroma, dac b = luma 0x45 reserved 0x00 0 0 5.17 s 0 1 5.31 s (default) 0x01 1 0 5.59 s (must be set for macrovision compliance) 0x46 sd mode register 4 ntsc color subcarrier adjust (falling edge of hs to start of color burst) 1 1 1 reserved 0 disabled sd prpb scale 1 enabled 0x00 0 disabled sd y scale 1 enabled 0 disabled sd hue adjust 1 enabled 0 disabled sd brightness 1 enabled 0 disabled sd luma ssaf gain 1 enabled reserved 0 0 must be written to this bit reserved 0 0 must be written to this bit 0x47 sd mode register 5 reserved 0 0 must be written to this bit reserved 0 0x00 reserved 0 0 must be written to this bit 0 disabled sd double buffering 1 enabled 0 8-bit input sd input format 1 16-bit input reserved 0 0 must be written to this bit 0 disabled sd digital noise reduction 1 enabled 0 disabled sd gamma control 1 enabled 0 gamma curve a 0x48 sd mode register 6 sd gamma curve 1 gamma curve b 0 0 disabled 0x00 0 1 ?11 ire 1 0 ?6 ire sd undershoot limiter 1 1 ?1.5 ire reserved 0 0 must be written to this bit 0 disabled sd black burst output on dac luma 1 enabled 0 0 disabled 0 1 4 clk cycles 1 0 8 clk cycles sd chroma delay 1 1 reserved reserved 0 0 must be written to this bit 0x49 sd mode register 7 reserved 0 0 must be written to this bit 1 ntsc color bar adjust should be set to 10 b for macrovision compliance.
preliminary technical data ADV7322 rev. pra | page 35 of 88 table 17. registers 0x4a to 0x58 sr7C sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset value 0 slave mode. sd slave/master mode 1 master mode. 0x08 0 0 mode 0. 0 1 mode 1. 1 0 mode 2. sd timing mode 1 1 mode 3. 0 enabled. sd blank input 1 disabled. 0 0 no delay. 0 1 2 clk cycles. 1 0 4 clk cycles. sd luma delay 1 1 6 clk cycles. 0 ?40 ire. sd min. luma value 1 ?7.5 ire. 0x4a sd timing register 0 sd timing reset x 0 0 0 0 0 0 0 a low-high-low transition will reset the internal sd timing counters. 0 0 t a = 1 clk cycle. 0x00 0 1 t a = 4 clk cycles. 1 0 t a = 16 clk cycles. sd hsync width 1 1 t a = 128 clk cycles. 0 0 t b = 0 clk cycle. 0 1 t b = 4 clk cycles. 1 0 t b = 8 clk cycles. sd hsync to vsync delay 1 1 t b = 18 clk cycles. x 0 t c = t b . sd hsync to vsync rising edge delay [mode 1 only] x 1 t c = t b + 32 s. 0 0 1 clk cycle. 0 1 4 clk cycles. 1 0 16 clk cycles. vsync width [mode 2 only] 1 1 128 clk cycles. 0 0 0 clk cycles. 0 1 1 clk cycle. 1 0 2 clk cycles. 0x4b sd timing register 1 hsync to pixel data adjust 1 1 3 clk cycles. 0x4c sd f sc register 0 1 x x x x x x x x subcarrier frequency bits 7C0. 0x1e 1 0x4d sd f sc register 1 x x x x x x x x subcarrier frequency bits 15C8. 0x7c 0x4e sd f sc register 2 x x x x x x x x subcarrier frequency bits 23C16. 0xf0 0x4f sd f sc register 3 x x x x x x x x subcarrier frequency bits 31C24. 0x21 0x50 sd f sc phase x x x x x x x x subcarrier phase bits 9C2. 0x00 0x51 sd closed captioning extended data on even fields x x x x x x x x extended data bits 7C0. 0x00 0x52 sd closed captioning extended data on even fields x x x x x x x x extended data bits 15C8. 0x00 0x53 sd closed captioning data on odd fields x x x x x x x x data bits 7C0. 0x00 0x54 sd closed captioning data on odd fields x x x x x x x x data bits 15C8. 0x00 0x55 sd pedestal register 0 pedestal on odd fields 17 16 15 14 13 12 11 10 setti ng any of these bits to 1 will disable pedestal on the line num- ber indicated by the bit settings. 0x00 0x56 sd pedestal register 1 pedestal on odd fields 25 24 23 22 21 20 19 18 0x00 0x57 sd pedestal register 2 pedestal on even fields 17 16 15 14 13 12 11 10 0x00 0x58 sd pedestal register 3 pedestal on even fields 25 24 23 22 21 20 19 18 0x00 1 for precise ntsc fsc, this valu e should be programmed to 0x1f. line 313 line 314 line 1 t b t a t c 05067-024 hsync vsync figure 47. timing register 1 in pal mode
ADV7322 preliminary technical data rev. pra | page 36 of 88 table 18. registers 0x59 to 0x64 sr7C sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset values sd cgms data 19 18 17 16 cgms data bits c19Cc16 0x00 0 disabled sd cgms crc 1 enabled 0 disabled sd cgms on odd fields 1 enabled 0 disabled sd cgms on even fields 1 enabled 0 disabled 0x59 sd cgms/wss 0 sd wss 1 enabled 13 12 11 10 9 8 cgms data bits c13Cc8, or wss data bits c13Cc8 0x00 0x5a sd cgms/wss 1 sd cgms/wss data 15 14 cgms data bits c15Cc14 0x00 0x5b sd cgms/wss 2 sd cgms/wss data 7 6 5 4 3 2 1 0 cgms/wss data bits c7Cc0 0x00 sd lsb for y scale value x x sd y scale bits 1C0 sd lsb for cb scale value x x sd cb scale bits 1C0 sd lsb for cr scale value x x sd cr scale bits 1C0 0x5c sd lsb register sd lsb for f sc phase x x subcarrier phase bits 1C0 0x5d sd y scale register sd y scale value x x x x x x x x sd y scale bits 7C2 0x00 0x5e sd cb scale register sd cb scale value x x x x x x x x sd cb scale bits 7C2 0x00 0x5f sd cr scale register sd cr scale value x x x x x x x x sd cr scale bits 7C2 0x00 0x60 sd hue register sd hue adjust value x x x x x x x x sd hue adjust bits 7C0 0x00 sd brightness value x x x x x x x sd brightness bits 6C0 0x00 0 disabled line 23 0x61 sd brightness/ wss sd blank wss data 1 enabled 0 0 0 0 0 0 0 0 ?4 db 0 0 0 0 0 1 1 0 0 db 0x62 sd luma ssaf sd luma ssaf gain/attenuation 0 0 0 0 1 1 0 0 +4 db 0x00 0 0 0 0 no gain 0x00 0 0 0 1 +1/16 [C1/8] 0 0 1 0 +2/16 [C2/8] 0 0 1 1 +3/16 [C3/8] 0 1 0 0 +4/16 [C4/8] 0 1 0 1 +5/16 [C5/8] 0 1 1 0 +6/16 [C6/8] 0 1 1 1 +7/16 [C7/8] coring gain border 1 0 0 0 +8/16 [C1] in dnr mode, the values in brackets apply. 0 0 0 0 no gain 0 0 0 1 +1/16 [C1/8] 0 0 1 0 +2/16 [C2/8] 0 0 1 1 +3/16 [C3/8] 0 1 0 0 +4/16 [C4/8] 0 1 0 1 +5/16 [C5/8] 0 1 1 0 +6/16 [C6/8] 0 1 1 1 +7/16 [C7/8] 0x63 sd dnr 0 coring gain data 1 0 0 0 +8/16 [C1] 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 62 dnr threshold 1 1 1 1 1 1 63 0x00 0 2 pixels border area 1 4 pixels 0 8 pixels 0x64 sd dnr 1 block size control 1 16 pixels
preliminary technical data ADV7322 rev. pra | page 37 of 88 table 19. registers 0x65 to 0x7c sr7C sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset values 0 0 1 filter a 0 1 0 filter b 0 1 1 filter c dnr input select 1 0 0 filter d 0x00 0 dnr mode dnr mode 1 dnr sharpness mode 0 0 0 0 0 pixel offset 0 0 0 1 1 pixel offset 1 1 1 0 14 pixel offset 0x65 sd dnr 2 dnr block offset 1 1 1 1 15 pixel offset 0x66 sd gamma a sd gamma curve a data points x x x x x x x x a0 0x00 0x67 sd gamma a sd gamma curve a data points x x x x x x x x a1 0x00 0x68 sd gamma a sd gamma curve a data points x x x x x x x x a2 0x00 0x69 sd gamma a sd gamma curve a data points x x x x x x x x a3 0x00 0x6a sd gamma a sd gamma curve a data points x x x x x x x x a4 0x00 0x6b sd gamma a sd gamma curve a data points x x x x x x x x a5 0x00 0x6c sd gamma a sd gamma curve a data points x x x x x x x x a6 0x00 0x6d sd gamma a sd gamma curve a data points x x x x x x x x a7 0x00 0x6e sd gamma a sd gamma curve a data points x x x x x x x x a8 0x00 0x6f sd gamma a sd gamma curve a data points x x x x x x x x a9 0x00 0x70 sd gamma b sd gamma curve b data points x x x x x x x x b0 0x00 0x71 sd gamma b sd gamma curve b data points x x x x x x x x b1 0x00 0x72 sd gamma b sd gamma curve b data points x x x x x x x x b2 0x00 0x73 sd gamma b sd gamma curve b data points x x x x x x x x b3 0x00 0x74 sd gamma b sd gamma curve b data points x x x x x x x x b4 0x00 0x75 sd gamma b sd gamma curve b data points x x x x x x x x b5 0x00 0x76 sd gamma b sd gamma curve b data points x x x x x x x x b6 0x00 0x77 sd gamma b sd gamma curve b data points x x x x x x x x b7 0x00 0x78 sd gamma b sd gamma curve b data points x x x x x x x x b8 0x00 0x79 sd gamma b sd gamma curve b data points x x x x x x x x b9 0x00 0x7a sd brightness detect sd brightness value x x x x x x x x read only field count x x x read only 0x8x reserved 0 reserved reserved 0 reserved reserved 0 reserved 0x7b field count register revision code 1 0 read only 0x7c reserved reserved 0x00
ADV7322 preliminary technical data rev. pra | page 38 of 88 table 20. registers 0x7d to 0x91 sr7- sr0 register bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reset values 0x7d reserved 0x7e reserved 0x7f reserved 0x80 macrovision mv control bits x x x x x x x x 0x00 0x81 macrovision mv control bits x x x x x x x x 0x00 0x82 macrovision mv control bits x x x x x x x x 0x00 0x83 macrovision mv control bits x x x x x x x x 0x00 0x84 macrovision mv control bits x x x x x x x x 0x00 0x85 macrovision mv control bits x x x x x x x x 0x00 0x86 macrovision mv control bits x x x x x x x x 0x00 0x87 macrovision mv control bits x x x x x x x x 0x00 0x88 macrovision mv control bits x x x x x x x x 0x00 0x89 macrovision mv control bits x x x x x x x x 0x00 0x8a macrovision mv control bits x x x x x x x x 0x00 0x8b macrovision mv control bits x x x x x x x x 0x00 0x8c macrovision mv control bits x x x x x x x x 0x00 0x8d macrovision mv control bits x x x x x x x x 0x00 0x8e macrovision mv control bits x x x x x x x x 0x00 0x8f macrovision mv control bits x x x x x x x x 0x00 0x90 macrovision mv control bits x x x x x x x x 0x00 0x91 macrovision mv control bit 0 0 0 0 0 0 0 x 0 must be written to these bits 0x00
preliminary technical data ADV7322 rev. pra | page 39 of 88 input configuration note that the ADV7322 defaults to simultaneous standard definition and progressive scan upon power-up (address[0x01]: input mode = 011). standard definition only address[0x01]: input mode = 000 the 8-bit multiplexed input data is input on pins s7 to s0 (or pins y7 to y0, depending on register address 0x01, bit 7), with s0 being the lsb in 8-bit input mode (see table 21). input standards supported are itu-r bt.601/656. in 16-bit input mode, the y pixel data is input on pins s7 to s0 and crcb data is input on pins y7 to y0 (see table 21). 16-bit mode operation when register 0x01 bit 7 = 0, crcb data is input on the y bus and y data is input on the s bus. when register 0x01 bit 7 = 1, crcb data is input on the c bus and y data is input on y bus. the 27 mhz clock input must be input on pin clkin_a. input sync signals are input on the s_vsync , s_hsync , and s_blank pins. table 21. sd 8-bit and 16-bit configuration configuration parameter 8-bit mode 16-bit mode register 0x01, bit 7 = 0 y bus crcb s bus 656/601, ycrcb y c bus register 0x01, bit 7 = 1 y bus 656/601, ycrcb y s bus c bus crcb mpeg2 decoder clkin_a s[7:0] or y[7:0]* 27mhz 3 8 ycrcb ADV7322 *selected by address 0x01 bit 7 05067-025 s_vsync, s_hsync, s_blank figure 48. sd only input mode progressive scan only or hdtv only address[0x01]: input mode = 001 or 010, respectively ycrcb progressive scan, hdtv, or any other hd ycrcb data can be input in 4:2:2 or 4:4:4. in 4:2:2 input mode, the y data is input on pins y7 to y0 and the crcb data is input on pins c7 to c0. in 4:4:4 input mode, y data is input on pins y7 to y0, cb data is input on pins c7 to c0, and cr data is input on pins s7 to s0. if the ycrcb data does not conform to smpte 293m (525p), itu-r bt.1358m (625p), smpte 274m[1080i], smpte 296m[720p], smpte 240m(1035i) or bta-t1004/1362, the async timing mode must be used. rgb data can only be input in 4:4:4 format in ps input mode or in hdtv input mode when hd rgb input is enabled. g data is input on pins y7 to y0, r data is input on pins s7 to s0, and b data is input on pins c7 to c0. the clock signal must be input on pin clkin_a. mpeg2 decoder clkin_a c[7:0] 8 cb s[7:0] y[7:0] interlaced to progressive ycrcb 8 cr 8 y 3 27mhz ADV7322 05067-026 p_vsync, p_hsync, p_blank figure 49. progressive scan input mode simultaneous standard definition and progressive scan or hdtv address[0x01]: input mode 011 (sd 8-bit, ps 16-bit) or 101 (sd and hd, sd oversampled), 110 (sd and hd, hd oversampled), respectively ycrcb, ps, hdtv, or any other hd data must be input in 4:2:2 format. in 4:2:2 input mode, the hd y data is input on pins y7 to y0 and the hd crcb data is input on pins c7 to c0. if ps 4:2:2 data is interleaved onto a single 10-bit bus, pins y7 to y0 are used for the input port. the input data is to be input at 27 mhz, with the data being clocked on the rising and falling edge of the input clock. the input mode register at address 0x01 is set accordingly. if the ycrcb data does not conform to smpte 293m (525p), itu-r bt.1358m (625p), smpte 274m[1080i], smpte 296m[720p], smpte 240m(1035i) or bta-t1004, the async timing mode must be used. the 8- bit standard definition data must be compliant with itu-r bt.601/656 in 4:2:2 format. standard definition data is input on pins s7 to s0, with s0 being the lsb. the clock input for sd must be input on clkin_a and the clock input for hd/ps must be input on clkin_b. synchronization signals are optional. sd syncs are input on pins s_vsync , s_hsync , and s_blank . hd syncs on pins p_vsync , p_hsync , and p_blank .
ADV7322 preliminary technical data rev. pra | page 40 of 88 clkin_a clkin_b mpeg2 decoder 3 27mhz 8 ycrcb interlaced to progressive 8 crcb 8 y 3 27mhz s[7:0] c[7:0] y[7:0] ADV7322 05067-027 s_vsync, s_hsync, s_blank p_vsync, p_hsync, p_blank figure 50. simultaneous ps and sd input clkin_a clkin_b sdtv decoder 3 27mhz 8 ycrcb 8 crcb 8 y 3 74.25mhz 1080i or 720p or 1035i s[7:0] c[7:0] y[7:0] ADV7322 hdtv decoder 05067-028 s_vsync, s_hsync, s_blank p_vsync, p_hsync, p_blank figure 51. simultaneous hd and sd input if in simultaneous sd/hd input mode and the two clock phases differ by less than 9.25 ns or more than 27.75 ns, the clock align bit [address 0x01, bit 3] must be set accordingly. if the application uses the same clock source for both sd and ps, the clock align bit must be set since the phase difference between both inputs is less than 9.25 ns. clkin_ a clkin_b 05067-029 t delay < 9.25ns or t delay > 27.75ns figure 52. clock phase with two input clocks progressive scan at 27 mhz (dual edge) or 54 mhz address[0x01]: input mode 100 or 111, respectively ycrcb progressive scan data can be input at 27 mhz or 54 mhz. the input data is interleaved onto a single 8-bit bus and is input on pins y7 to y0. when a 27 mhz clock is supplied, the data is clocked in on the rising and falling edge of the input clock and clock edge [address 0x01, bit 1] must be set accordingly. table 22 provides an overview of all possible input configurations. figure 53, figure 54, and figure 55 show the possible conditions: (a) cb data on the rising edge; and (b) y data on the rising edge. ff 00 00 xy y0 y1 cr0 clkin_b clockedgeaddress0x00bit1shouldbesetto0inthiscase. y7?y0 cb0 05067-030 figure 53. input sequence in ps bit interleaved mode (eav/sav) ff 00 00 xy cb0 cr0 y1 clkin_b y7?y0 y0 clock edge address 0x00 bit 1 should be set to 1 in this case. 05067-031 figure 54. input sequence in ps bit interleaved mode (eav/sav) pixel input data ff 00 00 xy cb0 y0 y1 cr0 clkin_b with a 54mhz clock, the data is latched on every rising edge. 05067-032 figure 55. input sequence in ps bit interleaved mode (eav/sav) mpeg2 decoder clkin_a y[7:0] interlaced to progressive ycrcb 8 3 27mhz or 54mhz ycrcb ADV7322 p_vsync, p_hsync, p_blank 05067-033 figure 56. 10-bit ps at 27 mhz or 54 mhz
preliminary technical data ADV7322 rev. pra | page 41 of 88 table 22. input configurations input format total bits input video input pins subaddress register setting 0x01 0x00 ycrcb s7Cs0 [msb = s7] 0x48 0x00 0x01 0x80 8 4:2:2 ycrcb y7Cy0 [msb = y7] 0x48 0x00 y s7Cs0 [msb = s7] 0x01 0x00 4:2:2 crcb y7Cy20[msb = y7] 0x48 0x08 y y7Cy0 [msb = y7] 0x01 0x80 itu-r bt.656 (4 options available) see table 21 16 4:2:2 crcb c7Cc0 [msb = y7] 0x48 0x00 0x01 0x10 8 [27 mhz clock] 4:2:2 ycrcb y7Cy0 [msb = y7] 0x13 0x40 0x01 0x70 8 [54 mhz clock] 4:2:2 ycrcb y7Cy0 [msb = y7] 0x13 0x40 y y7Cy0 [msb = y7] 0x01 0x10 16 4:2:2 crcb c7Cc0 [msb = c7] 0x13 0x40 y y7Cy0 [msb = y7] 0x01 0x10 cb c7Cc0 [msb = c7] ps only 24 4:4:4 cr s7Cs0 [msb = s7] 0x13 0x00 y y7Cy0 [msb = y7] 0x01 0x20 16 4:2:2 crcb c7Cc0 [msb = c7] 0x13 0x40 y y7Cy0 [msb = y7] 0x01 0x20 cb c7Cc0 [msb = c7] hdtv only 24 4:4:4 cr s7Cs0 [msb = s7] 0x13 0x00 g y7Cy0 [msb = y7] 0x01 0x10 or 0x20 b c7Cc0 [msb = c7] 0x13 0x00 hd rgb 24 4:4:4 r s7Cs0 [msb = s7] 0x15 0x02 8 (sd) 4:2:2 ycrcb s7Cs0 [msb = s7] 0x01 0x40 0x13 0x40 itu-r bt.656 and ps 8 (ps) 4:2:2 ycrcb y7Cy0 [msb = y7] 0x48 0x00 8 4:2:2 ycrcb s7Cs0 [msb = s7] 0x01 0x30, 0x50, or 0x60 y y7Cy0 [msb = y7] 0x13 0x40 itu-r bt.656 and ps or hdtv 16 4:2:2 crcb c7Cc0 [msb = c7] 0x48 0x00
ADV7322 preliminary technical data rev. pra | page 42 of 88 features output configuration table 23, table 24, and table 25 demonstrate what output signals are assigned to the dacs when the control bits are set accordi ngly. table 23. output configuration in sd only mode rgb/yuv output 0x02, bit 5 sd dac output 1 0x42, bit 2 sd dac output 2 0x42, bit 1 dac a dac b dac c dac d dac e dac f 0 0 0 cvbs luma chroma g b r 0 0 1 g b r cvbs luma chroma 0 1 0 g luma chroma cvbs b r 0 1 1 cvbs b r g luma chroma 1 0 0 cvbs luma chroma y u v 1 0 1 y u v cvbs luma chroma 1 1 0 y luma chroma cvbs u v 1 1 1 cvbs u v y luma chroma luma/chroma swap 0x44, bit 7 0 table as above 1 table above with all luma/chroma instances swapped table 24. output configuration in hd/ps only mode hd/ps input format hd/ps rgb input 0x15, bit 1 rgb/yprpb output 0x02, bit 5 hd/ps color swap 0x15, bit 3 dac a dac b dac c dac d dac e dac f ycrcb 4:2:2 0 0 0 n/a n/a n/a g b r ycrcb 4:2:2 0 0 1 n/a n/a n/a g r b ycrcb 4:2:2 0 1 0 n/a n/a n/a y pb pr ycrcb 4:2:2 0 1 1 n/a n/a n/a y pr pb ycrcb 4:4:4 0 0 0 n/a n/a n/a g b r ycrcb 4:4:4 0 0 1 n/a n/a n/a g r b ycrcb 4:4:4 0 1 0 n/a n/a n/a y pb pr ycrcb 4:4:4 0 1 1 n/a n/a n/a y pr pb rgb 4:4:4 1 0 0 n/a n/a n/a g b r rgb 4:4:4 1 0 1 n/a n/a n/a g r b rgb 4:4:4 1 1 0 n/a n/a n/a g b r rgb 4:4:4 1 1 1 n/a n/a n/a g r b table 25. output configuration in simultaneous sd and hd/ps only mode input formats rgb/yprpb output 0x02, bit 5 hd/ps color swap 0x15, bit 3 dac a dac b dac c dac d dac e dac f itu-r.bt656 and hd ycrcb in 4:2:2 0 0 cvbs luma chroma g b r itu-r.bt656 and hd ycrcb in 4:2:2 0 1 cvbs luma chroma g r b itu-r.bt656 and hd ycrcb in 4:2:2 1 0 cvbs luma chroma y pb pr itu-r.bt656 and hd ycrcb in 4:2:2 1 1 cvbs luma chroma y pr pb
preliminary technical data ADV7322 rev. pra | page 43 of 88 hd async timing mode [subaddress 0x10, bits 3 and 2] for any input data that does not conform to the standards selectable in input mode, subaddress 0x10, asynchronous timing mode can be used to interface to the ADV7322. timing control signals for hsync , vsync , and blank must be programmed by the user. macrovision and programmable oversampling rates are not available in async timing mode. in async mode, the pll must be turned off [subaddress 0x00, bit 1 = 1]. register 0x10 should be programmed to 0x01. figure 57 and figure 58 show examples of how to program the ADV7322 to accept a high definition standard other than smpte 293m, smpte 274m, smpte 296m, or itu-r bt.1358. table 26 must be followed when programming the control signals in async timing mode. for standards that do not require a trisync level, p_blank must be tied low at all times. table 26. async timing mode truth table p_hsync p_vsync p_blank 1 reference reference in figure 57 and figure 58 1 > 0 0 0 or 1 50% point of falling edge of trilevel horizontal sync signal a 0 0 > 1 0 or 1 25% point of rising edge of trilevel horizontal sync signal b 0 > 1 0 or 1 0 50% point of falling edge of trilevel horizontal sync signal c 1 0 or 1 0 > 1 50% start of active video d 1 0 or 1 1 > 0 50% end of active video e 1 when async timing mode is enabled, p_blank , pin 25, becomes an active high input. p_blank is set to active low at address 0x10, bit 6. clk active video programmable input timing analog output 81 66 66 243 1920 horizontal sync e d c b a set address 0x14, bit 3 = 1 05067-034 p_hsync p_vsync p_blank figure 57. async timing modeprogramming inpu t control signals for smpte 295m compatibility active video 0 1 horizontal sync e d c b a clk s et address 0x1 4 bit 3 = 1 analog output 05067-035 p_vsync p_blank p_hsync figure 58. async timing modeprogramming in put control signals for bilevel sync signal
ADV7322 preliminary technical data rev. pra | page 44 of 88 hd timing reset a timing reset is achieved by toggling the hd timing reset control bit [subaddress 0x14, bit 0] from 0 to 1. in this state the horizontal and vertical counters will remain reset. when this bit is set back to 0, the internal counters will commence counting again. the minimum time the pin has to be held high is one clock cycle; otherwise, this reset signal might not be recognized. this timing reset applies to the hd timing counters only. sd real-time control, subcarrier reset, and timing reset [subaddress 0x44, bits 2 and 1] together with the rtc_scr_tr pin and sd mode register 3 [address 0x44, bits 1 and 2], the ADV7322 can be used in (a) timing reset mode, (b) subcarrier phase reset mode, or (c) rtc mode. a. a timing reset is achieved in a low-to-high transition on the rtc_scr_tr pin (pin 31). in this state, the horizontal and vertical counters will remain reset. upon releasing this pin (set to low), the internal counters will commence counting again, the field count will start on field 1, and the subcarrier phase will be reset. the minimum time the pin must be held high is one clock cycle; otherwise, this reset signal might not be recognized. this timing reset applies to the sd timing counters only. b. in subcarrier phase reset, a low-to-high transition on the rtc_scr_tr pin (pin 31) will reset the subcarrier phase to zero on the field following the subcarrier phase reset when the sd rtc/tr/scr control bits at address 0x44 are set to 01. this reset signal must be held high for a minimum of one clock cycle. since the field counter is not reset, it is recommended that the reset signal is applied in field 7 [pal] or field 3 [ntsc]. the reset of the phase will then occur on the next field, i.e., field 1, being lined up correctly with the internal counters. the field count register at address 0x7b can be used to identify the number of the active field. c. in rtc mode, the ADV7322 can be used to lock to an external video source. the real-time control mode allows the ADV7322 to automatically alter the subcarrier frequency to compensate for line length variations. when the part is connected to a device that outputs a digital data stream in the rtc format, such as an adv7183a video decoder (see figure 61), the part will automatically change to the compensated subcarrier frequency on a line by line basis. this digital data stream is 67 bits wide and the subcarrier is contained in bits 0 to 21. each bit is two clock cycles long. write 0x00 into all four subcarrier frequency registers when this mode is used. display no timing reset applied timing reset applied start of field 4 or 8 f sc phase = field 4 or 8 f sc phase = field 1 timing reset pulse 307 310 307 12345 67 21 313 320 display start of field 1 05067-036 figure 59. timing reset timing diagram
preliminary technical data ADV7322 rev. pra | page 45 of 88 no f sc reset applied f sc phase = field 4 or 8 307 310 313 320 display start of field 4 or 8 f sc reset applied f sc reset pulse f sc phase = field 1 307 310 313 320 display start of field 4 or 8 05067-037 figure 60. subcarrier reset timing diagram lcc1 gll p17?p10 adv7183a video decoder composite video 1 clkin_a rtc_scr_tr dac a dac b dac c dac d dac e dac f y7?y0/s7?s0 5 rtc low h/l transition count start 128 time slot 01 13 0 14 bits subcarrier phase 14 21 19 f sc pll increment 2 valid sample invalid sample 6768 4bits reserved 0 sequence bit 3 reset bit 4 reserved ADV7322 notes 1 i.e., vcr or cable 2 f sc pll increment is 22 bits long. value loaded into ADV7322 f sc ddsregisterisf sc pll increments bits 21:0 plus bits 0:9 of subcarrier frequency registers. all zeros should be written to the subcarrier frequency registers of the ADV7322. 3 sequence bit pal: 0 = line normal, 1 = line inverted ntsc: 0 = no change 4 reset ADV7322 dds 5 selected by register address 0x01 bit 7 05067-038 8/line locked clock 5bits reserved figure 61. rtc timing and connections
ADV7322 preliminary technical data rev. pra | page 46 of 88 reset sequence a reset is activated with a high-to-low transition on the reset pin [pin 33] according to the timing specifications. the ADV7322 will revert to the default output configuration. figure 62 illustrates the reset timing sequence. sd vcr ff/rw sync [subaddress 0x42, bit 5] in dvd record applications where the encoder is used with a decoder, the vcr ff/rw sync control bit can be used for nonstandard input video, i.e., in fast forward or rewind modes. in fast forward mode, the sync information at the start of a new field in the incoming video usually occurs before the correct number of lines/fields is reached; in rewind mode, this sync signal usually occurs after the total number of lines/fields is reached. conventionally this means that the output video will have corrupted field signals, one generated by the incoming video and one generated when the internal lines/field counters reach the end of a field. when the vcr ff/rw sync control is enabled [subaddress 0x42, bit 5], the lines/fields counters are updated according to the incoming vsync signal, and the analog output matches the incoming vsync signal. this control is available in all slave timing modes except slave mode 0. xxxxxx xxxxxx off digital timing signals suppressed valid video timing active reset digital timing dacs a, b, c pixel data valid 05067-039 figure 62. reset timing sequence
preliminary technical data ADV7322 rev. pra | page 47 of 88 vertical blanking interval the ADV7322 accepts input data that contains vbi data [cgms, wss, vits, and so on] in sd and hd modes. for smpte 293m [525p] standards, vbi data can be inserted on lines 13 to 42 of each frame, or on lines 6 to 43 for the itu-r bt.1358 [625p] standard. for sd ntsc this data can be present on lines 10 to 20, and in pal on lines 7 to 22. if vbi is disabled [address 0x11, bit 4 for hd; address 0x43, bit 4 for sd], vbi data is not present at the output and the entire vbi is blanked. these control bits are valid in all master and slave modes. in slave mode 0, if vbi is enabled, the blanking bit in the eav/sav code is overwritten. it is possible to use vbi in this timing mode as well. in slave mode 1 or 2, the blank control bit must be set to enabled [address 0x4a, bit 3] to allow vbi data to pass through the ADV7322. otherwise, the ADV7322 automatically blanks the vbi to standard. if cgms is enabled and vbi is disabled, the cgms data will nevertheless be available at the output. see appendix 1copy generation management system. subcarrier frequency registers [subaddresses 0x4c to 0x4f] four 8-bit registers are used to set up the subcarrier frequency. the value of these registers is calculated using the equation 32 2 27 = line video one in cycles clk mhz of number line video one in periods subcarrier of number register frequency subcarrier where the sum is rounded to the nearest integer. for example, in ntsc mode 569408543 2 1716 5 . 227 re 32 = ? ? ? ? ? ? = value gister subcarrier where: subcarrier register value = 0x21f07c1f sd f sc register 0: 0x1f sd f sc register 1: 0x7c sd f sc register 2: 0xf0 sd f sc register 3: 0x21 see the mpu port description section for more details on how to access the subcarrier frequency registers. programming the f sc the subcarrier register value is shared across 4 f sc registers as shown above. to load the value into the encoder, users must write to the f sc registers in sequence, starting with f sc 0. the value is not loaded until the f sc 4 write is complete. note that the ADV7322 power-up value for f sc 0 = 0x1e. for precise ntsc f sc , write 0x1f to this register.
ADV7322 preliminary technical data rev. pra | page 48 of 88 square pixel timing mode [address 0x42, bit 4] in square pixel mode, the following timing diagrams apply. y c r y f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 f f 0 0 f f a b a b a b 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y c b y c r c b y c b y c r eav code sav code ancillary data (hanc) 4 clock 4 clock 272 clock 1280 clock 4 clock 4 clock 344 clock 1536 clock end of active video line start of active video line analog video input pixels ntsc/pal m system (525 lines/60hz) pal system (625 lines/50hz) y 05067-040 figure 63. eav/sav embedded timing field pixel data pal = 44 clock cycles ntsc = 44 clock cycles pal = 136 clock cycles ntsc = 208 clock cycles cb y cr y 05067-041 hsync blank figure 64. active pixel timing
preliminary technical data ADV7322 rev. pra | page 49 of 88 filters table 27 shows an overview of the programmable filters available on the ADV7322. table 27. selectable filters filter subaddress sd luma lpf ntsc 0x40 sd luma lpf pal 0x40 sd luma notch ntsc 0x40 sd luma notch pal 0x40 sd luma ssaf 0x40 sd luma cif 0x40 sd luma qcif 0x40 sd chroma 0.65 mhz 0x40 sd chroma 1.0 mhz 0x40 sd chroma 1.3 mhz 0x40 sd chroma 2.0 mhz 0x40 sd chroma 3.0 mhz 0x40 sd chroma cif 0x40 sd chroma qcif 0x40 sd uv ssaf 0x42 hd chroma input 0x13 hd sinc filter 0x13 hd chroma ssaf 0x13 sd internal filter response [subaddress 0x40 [7:2]; subaddress 0x42, bit 0] the y filter supports several different frequency responses including two low-pass responses, two notch responses, an extended (ssaf) response with or without gain boost attenuation, a cif response, and a qcif response. the uv filter supports several different frequency responses including six low-pass responses, a cif response, and a qcif response, as shown in figure 35 and figure 36. if sd ssaf gain is enabled, there is the option of 12 responses in the range ?4 db to +4 db [subaddress 0x47, bit 4]. the desired response can be chosen by the user by programming the correct value via the i 2 c [subaddress 0x62]. the variation of frequency responses are shown in figure 32 and figure 33. in addition to the chroma filters listed in table 27, the ADV7322 contains an ssaf filter specifically designed for and applicable to the color difference component outputs, u and v. this filter has a cutoff frequency of about 2.7 mhz and C40 db at 3.8 mhz, as shown in figure 65. this filter can be controlled with address 0x42, bit 0. frequency (mhz) 0 gain (db) ?10 ?30 ?50 ?60 ?20 ?40 6 5 4 3 2 1 0 05067-044 extended uv filter mode figure 65. uv ssaf filter if this filter is disabled, the selectable chroma filters shown in table 28 can be used for the cvbs or luma/chroma signal. table 28. internal filter specifications filter pass-band ripple 1 (db) 3 db bandwidth 2 (mhz) luma lpf ntsc 0.16 4.24 luma lpf pal 0.1 4.81 luma notch ntsc 0.09 2.3/4.9/6.6 luma notch pal 0.1 3.1/5.6/6.4 luma ssaf 0.04 6.45 luma cif 0.127 3.02 luma qcif monotonic 1.5 chroma 0.65 mhz monotonic 0.65 chroma 1.0 mhz monotonic 1 chroma 1.3 mhz 0.09 1.395 chroma 2.0 mhz 0.048 2.2 chroma 3.0 mhz monotonic 3.2 chroma cif monotonic 0.65 chroma qcif monotonic 0.5 1 pass-band ripple is the maximum fluctuation from the 0 db response in the pass band, measured in db. the pass band is defined to have 0 hz to fc (hz) frequency limits for a low-pass filter, and 0 hz to f1 (hz) and f2 (hz) to infinity for a notch filter, where fc, f1, and f2 are the ?3 db points. 2 3 db bandwidth refers to the ?3 db cutoff frequency.
ADV7322 preliminary technical data rev. pra | page 50 of 88 ps/hd sinc filter [subaddress 0x13, bit 3] frequency (mhz) 0.5 ?0.5 30 5 0 gain (db) 10 15 20 25 0.4 0.1 ?0.2 ?0.3 ?0.4 0.3 0.2 0 ?0.1 05067-042 figure 66. hd sinc filter enabled frequency (mhz) 0.5 ?0.5 30 5 0 gain (db) 10 15 20 25 0.4 0.1 ?0.2 ?0.3 ?0.4 0.3 0.2 0 ?0.1 05067-043 figure 67. hd sinc filter disabled color controls and rgb matrix hd y level, hd cr level, hd cb level [subaddresses 0x16 to 0x18] three 8-bit registers at addresses 0x16, 0x17, and 0x18 are used to program the output color of the internal hd test pattern generator, be it the lines of the cross hatch pattern or the uniform field test pattern. they are not functional as color controls on external pixel data input. for this purpose the rgb matrix is used. the standard used for the values for y and the color difference signals to obtain white, black, and the saturated primary and complementary colors conforms to the itu-r bt.601-4 standard. table 29 shows sample color values to be programmed into the color registers when output standard selection is set to eia 770.2. table 29. sample color values for eia 770.2 output standard selection sample color y value cr value cb value white 235 (eb) 128 (80) 128 (80) black 16 (10) 128 (80) 128 (80) red 81 (51) 240 (f0) 90 (5a) green 145 (91) 34 (22) 54 (36) blue 41 (29) 110 (6e) 240 (f0) yellow 210 (d2) 146 (92) 16 (10) cyan 170 (aa) 16 (10) 166 (a6) magenta 106 (6a) 222 (de) 202 (ca) rgb matrix [subaddresses 0x03 to 0x09] the internal rgb matrix automatically takes care of all ycrcb to rgb scaling according to the input standard programmed in the device as selected by input mode register 0x01 [6:4]. table 30 shows the options available in this matrix. note that it is not possible to do a color space conversion from rgb-in to yprpb-out. also, it is not possible to input sd rgb. table 30. matrix conversion options hdtv/sd/ps input output reg 0x02,bit 5 (yuv/rgb out) reg 0x15, bit 1 (rgb in/ycrcb in, ps/hd only) ycrcb yprpb 1 0 ycrcb rgb 0 0 rgb rgb 0 1 manual rgb matrix adjust feature normally, there is no need to enable this feature in register 0x02, bit 3, because the rgb matrix automatically takes care of color space conversion depending on the input mode chosen (sd/ps,hd) and the polarity of rgb/yprpb output in register 0x02, bit 5 (see table 30). for this reason, manual rgb matrix adjust feature is turned off by default. the manual rgb matrix adjust feature is used in progressive scan and high definition modes only and is used for custom coefficient manipulation. when the manual rgb matrix adjust feature is enabled, the default values in registers 0x05 to 0x09 are correct for hdtv color space only. the color components are converted according to the 1080i and 720p standards [smpte 274m, smpte 296m]: r = y + 1.575 pr g = y ? 0.468 pr ? 0.187 pb b = y + 1.855 pb
preliminary technical data ADV7322 rev. pra | page 51 of 88 this is reflected in the preprogrammed values for gy = 0x138b, gu = 0x93, gv = 0x3b, bu = 0x248, and rv = 0x1f0. again if rgb matrix is enabled and another input standard is used (sd or ps), the scale values for gy, gu, gv, bu, and rv must be adjusted according to this input standard color space. the user should consider the fact that the color component conversion might use different scale values. for example, smpte 293m uses the following conversion: r = y + 1.402 pr g = y C 0.714 pr C 0.344 pb b = y + 1.773 pb the manual rgb matrix adjust feature can be used to control the hd output levels in cases where the video output does not conform to the standard due to altering the dac output stages such as termination resistors. the programmable rgb matrix is used for external hd/ps data and is not functional when internal test patterns are enabled. adjusting registers 0x05 to 0x09 requires the manual rgb matrix adjust to be enabled [register 0x02, bit 3 =1]. programming the rgb matrix if custom manipulation of coefficients is required, the rgb matrix is enabled in address 0x02, bit 3. the output should be set to rgb [address 0x02, bit 5], sync on prpb should be disabled (default) [address 0x15, bit 2], and sync on rgb is optional [address 0x02, bit 4]. gy at addresses 0x03 and 0x05 control the green signal output levels. bu at addresses 0x04 and 0x08 control the blue signal output levels, and rv at addresses 0x04 and 0x09 control the red signal output levels. to control yprpb output levels, yuv output should be enabled [address 0x02, bit 5]. in this case gy [address 0x05; address 0x03, bits 0 and 1] is used for the y output, rv [address 0x09; address 0x04, bits 0 and 1] is used for the pr output, and bu [address 0x08; address 0x04, bits 2 and 3] is used for the pb output. if rgb output is selected, the rgb matrix scaler uses the following equations: g = gy y + gu pb + gv pr b = gy y + bu pb r = gy y + rv pr if yprpb output is selected, the following equations are used: y = gy y u = bu pb v = rv pr upon power-up, the rgb matrix is programmed with the default values in table 31. table 31. rgb matrix default values address default 0x03 0x03 0x04 0xf0 0x05 0x4e 0x06 0x0e 0x07 0x24 0x08 0x92 0x09 0x7c when the manual rgb matrix adjust feature is not enabled, the ADV7322 automatically scales ycrcb inputs to all standards supported by this part as selected by input mode register 0x01 [6:4]. sd luma and color control [subaddresses 0x5c, 0x5d, 0x 5e, 0x 5f] sd y scale, sd cr scale, and sd cb scale are three 10-bit-wide control registers that scale the y, cb, and cr output levels. each of these registers represents the value required to scale the cb or cr level from 0.0 to 2.0 and the y level from 0.0 to 1.5 of its initial level. the value of these 10 bits is calculated using the following equation: y, cr, or cb s calar value = scale factor 512 for example, scale factor = 1.18 y, cb, or cr s cale value = 1.18 512 = 665.6 y, cb, or cr s cale value = 665 (rounded to the nearest integer) y, cb, or cr scale value = 1010 0110 01b address 0x5c, sd lsb register = 0x15 address 0x5d, sd y scale register = 0xa6 address 0x5e, sd cb scale register = 0xa6 address 0x5f, sd cr scale register = 0xa6 note that this feature affects all interlaced output signals, i.e., cvbs, y-c, yprpb, and rgb. sd hue adjust value [subaddress 0x60] the hue adjust value is used to adjust the hue on the composite and chroma outputs. these eight bits represent the value required to vary the hue of the video data, i.e., the variance in phase of the subcarrier during active video with respect to the phase of the subcarrier during the color burst. the ADV7322 provides a range of 22.5
ADV7322 preliminary technical data rev. pra | page 52 of 88 increments of 0.17578125. for normal operation (zero adjustment), this register is set to 0x80. values 0xff and 0x00 represent the upper and lower limits (respectively) of adjustment attainable. hue adjust () = 0.17578125 ( hcr d ? 128) for positive hue adjust value. for example, to adjust the hue by +4, write 0x97 to the hue adjust value register: 97 x 0 105 128 17578125 . 0 4 = = + ? ? ? ? ? ? d . where the sum is rounded to the nearest integer. to adjust the hue by ?4, write 0x69 to the hue adjust value register: 69 x 0 105 128 17578125 . 0 4 = = + ? ? ? ? ? ? ? d where the sum is rounded to the nearest integer. sd brightness control [subaddress 0x61] the brightness is controlled by adding a programmable setup level onto the scaled y data. this brightness level may be added onto the scaled y data. for ntsc with pedestal, the setup can vary from 0 ire to 22.5 ire. for ntsc without pedestal and pal, the setup can vary from ?7.5 ire to +15 ire. the brightness control register is an 8-bit register. seven bits of this 8-bit register are used to control the brightness level. this brightness level can be a positive or negative value. for example, 1. to add +20 ire brightness level to an ntsc signal with pedestal , write 0x28 to address 0x61, sd brightness. 0x[ sd brightness value ] = 0x[ ire value 2.015631] = 0x[20 2.015631] = 0x[40.31262] = 0x28 2. to add C7 ire brightness level to a pal signal, write 0x72 to address 0x61, sd brightness. [ ire value| 2.075631 [7 2.015631] = [14.109417] = 0001110 b [0001110] into twos complement = [1110010] b = 0x72 table 32. brightness control values 1 setup level in ntsc with pedestal setup level in ntsc no pedestal setup level in pal sd brightness 22.5 ire 15 ire 15 ire 0x1e 15 ire 7.5 ire 7.5 ire 0x0f 7.5 ire 0 ire 0 ire 0x00 0 ire C7.5 ire C7.5 ire 0x71 1 values in the range from 0x3f to 0x 44 might result in an invalid output signal.
preliminary technical data ADV7322 rev. pra | page 53 of 88 sd brightness detect [subaddress 0x7a] the ADV7322 allows monitoring of the brightness level of the incoming video data. brightness detect is a read-only register. double buffering [subaddress 0x13, bit 7; subaddress 0x48, bit 2] double buffered registers are updated once per field on the falling edge of the vsync signal. double buffering improves the overall performance since modifications to register settings will not be made during active video, but takes effect on the start of the active video. double buffering can be activated on the following hd registers: hd gamma a and gamma b curves and hd cgms registers. double buffering can be activated on the following sd registers: sd gamma a and gamma b curves, sd y scale, sd u scale, sd v scale, sd brightness, sd closed captioning, and sd macrovision bits 5 to 0. ntsc without pedestal no setup value added positive setup value added 100 ire 0 ire negative setup value added ?7.5 ire +7.5 ire 05067-069 figure 68. examples of brightness control values
ADV7322 preliminary technical data rev. pra | page 54 of 88 programmable dac gain control dacs a, b, and c are controlled by reg 0a. dacs d, e, and f are controlled by reg 0b. the i 2 c control registers will adjust the output signal gain up or down from its absolute level. case b 700mv 300mv negative gain programmed in dac output level registers, subaddress 0x0a, 0x0b case a gain programmed in dac output leve l registers, subaddress 0x0a, 0x0b 700mv 300mv 05067-070 figure 69. programmable dac gainpositive and negative gain in case a, the video output signal is gained. the absolute level of the sync tip and blanking level both increase with respect to the reference video output signal. the overall gain of the signal is increased from the reference signal. in case b, the video output signal is reduced. the absolute level of the sync tip and blanking level both decrease with respect to the reference video output signal. the overall gain of the signal is reduced from the reference signal. the range of this feature is specified for 7.5% of the nominal output from the dacs. for example, if the output current of the dac is 4.33 ma, the dac tune feature can change this output current from 4.008 ma (?7.5%) to 4.658 ma (+7.5%). the reset value of the vid_out_ctrl registers is 0x00; therefore, nominal dac current is output. the following table is an example of how the output current of the dacs varies for a nominal 4.33 ma output current. table 33. dac gain control reg 0x0a or 0x0b dac current (ma) % gain note 0100 0000 (0x40) 4.658 7.5000% 0011 1111 (0x3f) 4.653 7.3820% 0011 1110 (0x3e) 4.648 7.3640% ... ... ... ... ... ... 0000 0010 (0x02) 4.43 0.0360% 0000 0001 (0x01) 4.38 0.0180% 0000 0000 (0x00) 4.33 0.0000% (i 2 c reset value, nominal) 1111 1111 (0xff) 4.25 ?0.0180% 1111 1110 (0xfe) 4.23 ?0.0360% ... ... ... ... ... ... 1100 0010 (0xc2) 4.018 ?7.3640% 1100 0001 (0xc1) 4.013 ?7.3820% 1100 0000 (0xc0) 4.008 ?7.5000% gamma correction [subaddresses 0x24 to 0x37 for hd, subaddresses 0x66 to 0x79 for sd] gamma correction is available for sd and hd video. for each standard, there are twenty 8-bit-wide registers. they are used to program the gamma correction curves a and b. hd gamma curve a is programmed at addresses 0x24 to 0x2d, and hd gamma curve b is programmed at 0x2e to 0x7. sd gamma curve a is programmed at addresses 0x66 to 0x6f, and sd gamma curve b is programmed at addresses 0x70 to 0x79. generally gamma correction is applied to compensate for the nonlinear relationship between signal input and brightness level output (as perceived on the crt). it can also be applied wherever nonlinear processing is used. gamma correction uses the function ( ) = in out signal signal where = gamma power factor. gamma correction is performed on the luma data only. the user may choose either of two curves, curve a or curve b. at any one time, only one of these curves can be used. the response of the curve is programmed at 10 predefined locations. in changing the values at these locations, the gamma curve can be modified. between these points, linear interpolation is used to generate intermediate values. considering the curve to have a total length of 256 points, the 10 locations are at 24, 32, 48, 64, 80, 96, 128, 160, 192, and 224. locations 0, 16, 240, and 255 are fixed and cannot be changed.
preliminary technical data ADV7322 rev. pra | page 55 of 88 for the length of 16 to 240, the gamma correction curve has to be calculated as follows: y = x where: y = gamma corrected output x = linear input signal = gamma power factor to program the gamma correction registers, calculate the seven values for y using the following formula: 16 ) 16 240 ( ) 16 240 ( ) 16 ( + ? ? ? ? ? ? ? ? = ? n n x y where: x ( n ? 16) = value for x along x axis at points n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224 y n = value for y along the y axis, which must be written into the gamma correction register for example, y 24 = [(8/224)0.5 224] + 16 = 58 y 32 = [(16/224)0.5 224] + 16 = 76 y 48 = [(32/224)0.5 224] + 16 = 101 y 64 = [(48/224)0.5 224] + 16 =120 y 80 = [(64 / 224)0.5 224] + 16 =136 y 96 = [(80 / 224)0.5 224] + 16 = 150 y 128 = [(112 / 224)0.5 224] + 16 = 174 y 160 = [(144 / 224)0.5 224] + 16 = 195 y 192 = [(176 / 224)0.5 224] + 16 = 214 y 224 = [(208 / 224)0.5 224] + 16 = 232 where the sum of each equation is rounded to the nearest integer. the gamma curves in figure 70 and figure 71 are examples only; any user-defined curve is acceptable in the range of 16 to 240. location 0 0 50 100 150 200 250 300 50 100 150 200 250 0.5 signal input gamma corrected amplitude signal output gamma correction block output to a ramp input 05067-071 figure 70. signal input (ramp) and signal output for gamma 0.5 location 0 0 50 100 150 200 250 300 50 100 150 200 250 gamma corrected amplitude gamma correction block to a ramp input for various gamma values 0.3 0.5 1.5 1.8 s i g n a l i n p u t 05067-072 figure 71. signal input (ramp) and selectable output curves
ADV7322 preliminary technical data rev. pra | page 56 of 88 hd sharpness filter and adaptive filter controls [subaddresses 0x20, 0x38 to 0x3d] there are three filter modes available on the ADV7322: sharpness filter mode and two adaptive filter modes. hd sharpness filter mode to enhance or attenuate the y signal in the frequency ranges shown in figure 72, the following register settings must be used: hd sharpness filter must be enabled and hd adaptive filter enable must be set to disabled. to select one of the 256 individual responses, the corresponding gain values, which range from C8 to +7, for each filter must be programmed into the hd sharpness filter gain register at address 0x20. hd adaptive filter mode the hd adaptive filter threshold a, b, and c registers, the hd adaptive filter gain 1, 2, and 3 registers, and the hd sharpness gain register are used in adaptive filter mode. to activate the adaptive filter control, the hd sharpness filter and the hd adaptive filter must be enabled. the derivative of the incoming signal is compared to the three programmable threshold values: hd adaptive filter threshold a, b, and c. the recommended threshold range is from 16 to 235, although any value in the range of 0 to 255 can be used. the edges can then be attenuat ed with the settings in hd adaptive filter gain 1, 2, and 3 registers and hd sharpness filter gain register. according to the settings of the hd adaptive filter mode control, there are two adaptive filter modes available: 1. mode a is used when adaptive filter mode is set to 0. in this case, filter b (lpf) will be used in the adaptive filter block. also, only the programmed values for gain b in the hd sharpness filter gain and hd adaptive filter gain 1, 2, and 3 are applied when needed. the gain a values are fixed and cannot be changed. 2. mode b is used when adaptive filter mode is set to 1. in this mode, a cascade of filter a and filter b is used. both settings for gain a and gain b in the hd sharpness filter gain and hd adaptive filter gain 1, 2, and 3 become active when needed. frequency (mhz) filter a response (gain ka) magnitude 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 frequency (mhz) filter b response (gain kb) magnitude 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 frequency (mhz) magnitude response (linear scale) 1.0 1.1 1.2 1.3 1.4 1.5 1.6 10 12 input s ignal: step frequency response in sharpness filter mode with ka = 3 and kb = 7 sharpness and adaptive filter control block 0 2 4 6 8 05067-073 figure 72. sharpness and adaptive filter control block
preliminary technical data ADV7322 rev. pra | page 57 of 88 hd sharpness filter and adaptive filter application examples hd sharpness filter application the hd sharpness filter can be used to enhance or attenuate the y video output signal. the following register settings were used to achieve the results shown in figure 73. input data was generated by an external signal source. table 34. sharpness control address register setting reference 1 0x00 0xfc 0x01 0x10 0x02 0x20 0x10 0x00 0x11 0x81 0x20 0x00 a 0x20 0x08 b 0x20 0x04 c 0x20 0x40 d 0x20 0x80 e 0x20 0x22 f 1 see figure 73. f e d a b c 1 r4 r2 ch1 500mv m 4.00 s ch1 all fields ref a 500mv 4.00 s 1 r2 r1 1 ch1 500mv m 4.00 s ch1 all fields ref a 500mv 4.00 s 1 05067-074 9.99978ms 9.99978ms figure 73. hd sharpness filter control with different gain settings for hs sharpness filter gain values
ADV7322 preliminary technical data rev. pra | page 58 of 88 adaptive filter control application figure 74 and figure 75 show typical signals to be processed by the adaptive filter control block. ? : 692mv @: 446mv ? : 332ns @: 12.8ms 05067-075 figure 74. input signal to adaptive filter control ? : 692mv @: 446mv ? : 332ns @: 12.8ms 05067-076 figure 75. output signal af ter adaptive filter control the register settings in table 35 were used to obtain the results shown in figure 75, i.e., to remove the ringing on the y signal. input data was generated by an external signal source. table 35. register settings for figure 76 address register setting 0x00 0xfc 0x01 0x38 0x02 0x20 0x10 0x00 0x11 0x81 0x15 0x80 0x20 0x00 0x38 0xac 0x39 0x9a 0x3a 0x88 0x3b 0x28 0x3c 0x3f 0x3d 0x64 when changing the adaptive filter mode to mode b [address 0x15, bit 6], the output shown in figure 76 can be obtained. ? : 674mv @: 446mv ? : 332ns @: 12.8ms 05067-077 figure 76. output signal from adaptive filter control sd digital noise reduction [subaddresses 0x63, 0x64, 0x65] dnr is applied to the y data only. a filter block selects the high frequency, low amplitude compon ents of the incoming signal [dnr input select]. the absolute value of the filter output is compared to a programmable threshold value ['dnr threshold control]. there are two dnr modes available: dnr mode and dnr sharpness mode. in dnr mode, if the absolute value of the filter output is smaller than the threshold, it is assumed to be noise. a programmable amount [coring gain border, coring gain data] of this noise signal will be subtracted from the original signal. in dnr sharpness mode, if the absolute value of the filter output is less than the programmed threshold, it is assumed to be noise, as before. otherwise, if the level exceeds the threshold, now being identified as a valid signal, a fraction of the signal [coring gain border, coring gain data] will be added to the original signal to boost high frequency components and sharpen the video image. in mpeg systems, it is common to process the video information in blocks of 8 pixels 8 pixels for mpeg2 systems, or 16 pixels 16 pixels for mpeg1 systems [block size control]. dnr can be applied to the resulting block transition areas that are known to contain noise. generally, the block transition area contains two pixels. it is possible to define this area to contain four pixels [border area]. it is also possible to compensate for variable block positioning or differences in ycrcb pixel timing with the use of the dnr block offset the digital noise reduction registers are three 8-bit registers. they are used to control the dnr processing.
preliminary technical data ADV7322 rev. pra | page 59 of 88 block size control border area block offset coring gain data coring gain border gain dnr control filter output > threshold? input filter block filter output < threshold dnr out + + main signal path add signal above threshold range from original signal dnr sharpness mode noise signal path y dat a input block size control border area block offset coring gain data coring gain border gain dnr control filter output < threshold? input filter block filter output > threshold dnr out main signal path subtract signal in threshold range from original signal dnr mode noise signal path y data input ? + 05067-078 figure 77. dnr block diagram coring gain border [address 0x63, bits 3 to 0] these four bits are assigned to the gain factor applied to border areas. in dnr mode, the range of gain values is 0 to 1 in increments of 1/8. this factor is applied to the dnr filter output, which lies below the set threshold range. the result is then subtracted from the original signal. in dnr sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. this factor is applied to the dnr filter output, which lies above the threshold range. the result is added to the original signal. coring gain data [address 0x63, bits 7 to 4] these four bits are assigned to the gain factor applied to the luma data inside the mpeg pixel block. in dnr mode, the range of gain values is 0 to 1 in increments of 1/8. this factor is applied to the dnr filter output, which lies below the set threshold range. the result is then subtracted from the original signal. in dnr sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. this factor is applied to the dnr filter output, which lies above the threshold range. the result is added to the original signal. oxxxxxxooxxxxxxo oxxxxxxooxxxxxxo oxxxxxxooxxxxxxo dnr27 ? dnr24 = 0x01 offset caused by variations in input timing apply border coring gain apply data coring gain 05067-079 figure 78. dnr offset control dnr threshold [address 0x64, bits 5 to 0] these six bits are used to define the threshold value in the range of 0 to 63. the range is an absolute value. border area [address 0x64, bit 6] when this bit is set to logic 1, the block transition area can be defined to consist of four pixels. if this bit is set to logic 0, the border transition area consists of two pixels, where one pixel refers to two clock cycles at 27 mhz. 720 485 pixels (ntsc) 8 8 pixel block 2-pixel border data 8 8 pixel block 05067-080 figure 79. dnr border area block size control [address 0x64, bit 7] this bit is used to select the size of the data blocks to be processed. setting the block size control function to logic 1 defines a 16 pixel 16 pixel data block, and logic 0 defines an 8 pixel 8 pixel data block, wher e one pixel refers to two clock cycles at 27 mhz. dnr input select control [address 0x65, bits 2 to 0] three bits are assigned to select the filter, which is applied to the incoming y data. the signal that lies in the pass band of the selected filter is the signal that will be dnr processed. figure 80 shows the filter responses selectable with this control.
ADV7322 preliminary technical data rev. pra | page 60 of 88 filter c filter b filter a filter d frequency (hz) 0 0.2 0.4 0.6 magnitude 0.8 1.0 05067-081 0 1 23 45 6 figure 80. dnr input select dnr mode control [address 0x65, bit 4] this bit controls the dnr mode selected. logic 0 selects dnr mode; logic 1 selects dnr sharpness mode. dnr works on the principle of defining low amplitude, high frequency signals as probable noise and subtracting this noise from the original signal. in dnr mode, it is possible to subtract a fraction of the signal that lies below the set threshold, assumed to be noise, from the original signal. the threshold is set in dnr register 1. when dnr sharpness mode is enabled, it is possible to add a fraction of the signal that lies above the set threshold to the original signal, since this data is assumed to be valid data and not noise. the overall effect is that the signal will be boosted (similar to using extended ssaf filter). block offset control [address 0x65, bits 7 to 4] four bits are assigned to this control, which allows a shift of the data block of 15 pixels maximum. consider the coring gain positions fixed. the block offset shifts the data in steps of one pixel such that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data. sd active video edge [subaddress 0x42, bit 7] when the active video edge feature is enabled, the first three pixels and the last three pixels of the active video on the luma channel are scaled so that maximum transitions on these pixels are not possible. the scaling factors are 1/8, 1/2, and 7/8. all other active video passes through unprocessed. sav/eav step edge control the ADV7322 has the capability of controlling fast rising and falling signals at the start and end of active video to minimize ringing. an algorithm monitors sav and eav and determines when the edges are rising or falling too fast. the result is reduced ringing at the start and end of active video for fast transitions. subaddress 0x42, bit 7 = 1, enables this feature. 100 ire 0 ire 100 ire 12.5 ire 87.5 ire 0 ire 50 ire luma channel with active video edge disabled luma channel with active video edge enabled 05067-082 figure 81. example of active video edge functionality
preliminary technical data ADV7322 rev. pra | page 61 of 88 volts 024 f2 l135 6 8 10 12 ire:flt ?50 0 0 50 100 0.5 05067-083 figure 82. address 0x42, bit 7 = 0 volts 02 ?2 4 6 8 10 12 f2 l135 ire:flt ?50 0 50 100 0 0.5 05067-084 figure 83. address 0x42, bit 7 = 1
ADV7322 preliminary technical data rev. pra | page 62 of 88 board design and layout dac termination and layout considerations the ADV7322 contains an on-board voltage reference. the ADV7322 can be used with an external v ref (ad1580). the r set resistors are connected between the r set pins and agnd and are used to control the full-scale output current and, therefore, the dac voltage output levels. for full-scale output, r set must have a value of 3040 ?. the rset values should not be changed. r load has a value of 300 ? for full-scale output. video output buffer and optional output filter output buffering on all six dacs is necessary to drive output devices, such as sd or hd monitors. analog devices produces a range of suitable op amps for this application, for example the ad8061. more information on line driver buffering circuits is given in the relevant op amps data sheets. an optional analog reconstruction low-pass filter (lpf) may be required as an anti-imaging filter if the ADV7322 is connected to a device that requires this filtering. the filter specifications vary with the application. table 36. external filter requirements application oversampling cutoff frequency (mhz) attenuation C50 db @ (mhz) sd 2 >6.5 20.5 sd 16 >6.5 209.5 ps 1 >12.5 14.5 ps 8 >12.5 203.5 hdtv 1 >30 44.25 hdtv 2 >30 118.5 560 ? 600 ? 3 4 1 22pf 600 ? dac output 75 ? bnc output 10 h 560 ? 05067-085 figure 84. example of output filter for sd, 16 oversampling 0 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ?30 ?60 ?90 ?120 ?150 ?180 ?210 ?240 1m 10m 100m frequency (hz) circuit frequency response 1g group delay (sec) phase (deg) magnitude (db) 21n 18n 15n 12n 9n 6n 3n 0 24n gain (db) 05067-086 figure 85. filter plot for output filter for sd, 16 oversampling 560 ? 3 4 1 6.8pf 600 ? 6.8pf 600 ? dac output 75 ? bnc output 4.7 ? 05067-087 figure 86. example of output filter for ps, 8 oversampling 82pf 33pf 75 ? dac output 220nh 470nh 500 ? 3 4 1 bnc output 500 ? 300 ? 3 4 1 75 ? 05067-088 figure 87. example of output filter for hdtv, 2 oversampling table 37. possible output rates from the ADV7322 input mode address 0x01, bits 6 to 4 pll address 0x00, bit 1 output rate (mhz) off 27 (2) sd only on 216 (16) off 27 (1) ps only on 216 (8) hdtv only off on 74.25 (1) 148.5 (2)
preliminary technical data ADV7322 rev. pra | page 63 of 88 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 1m 10m 100m 1g frequency (hz) circuit frequency response magnitude (db) group delay (sec) phase (deg) gain (db) 320 240 160 80 0 ?80 ?160 ?240 480 400 14n 12n 10n 8n 6n 4n 2n 0 18n 16n 05067-089 figure 88. filter plot for output filter for ps, 8 oversampling 0 ?10 ?20 ?30 ?40 ?50 ?60 480 360 240 120 0 ?120 ?240 18n 15n 12n 9n 6n 3n 0 1m 10m 100m 1g frequency (hz) circuit frequency response group delay (sec) phase (deg) magnitude (db) gain (db) 05067-090 figure 89. filter plot for output filter for hdtv, 2 oversampling pcb board layout the ADV7322 is optimally designed for lowest noise performance, both radiated and conducted noise. to complement the excellent noise performance of the ADV7322, it is imperative that great care be given to the pc board layout. the layout should be optimized for lowest noise on the ADV7322 power and ground lines. this can be achieved by shielding the digital inputs and providing good decoupling. the lead length between groups of v aa and agnd, v dd and dgnd, and v dd_io and gnd_io pins should be kept as short as possible to minimized inductive ringing. it is recommended that a 4-layer printed circuit board is used, with power and ground planes separating the layer of the signal carrying traces of the components and solder side layer. component placement should be carefully considered in order to separate noisy circuits, such as crystal clocks, high speed logic circuitry, and analog circuitry. there should be a separate analog ground plane and a separate digital ground plane. power planes should encompass a digital power plane and an analog power plane. the analog power plane should contain the dacs and all associated circuitry, v ref circuitry. the digital power plane should contain all logic circuitry. the analog and digital power planes should be individually connected to the common power plane at a single point through a suitable filtering device, such as a ferrite bead. dac output traces on a pcb should be treated as transmission lines. it is recommended that the dacs be placed as close as possible to the output connector, with the analog output traces being as short as possible (less than 3 inches). the dac termination resistors should be placed as close as possible to the dac outputs and should overlay the pcbs ground plane. as well as minimizing reflections, short analog output traces will reduce noise pickup due to neighboring digital circuitry. to avoid crosstalk between the dac outputs, it is recommended that as much space as possible be left between the tracks of the individual dac output pins. the addition of ground tracks between outputs is also recommended. supply decoupling noise on the analog power plane can be further reduced by the use of decoupling capacitors. optimum performance is achieved by the use of 10 nf and 0.1 f ceramic capacitors. each group of v aa , v dd , or v dd_io pins should be individually decoupled to ground. this should be done by placing the capacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance. a 1 f tantalum capacitor is recommended across the v aa supply in addition to 10 nf ceramic. see the circuit layout in figure 90. digital signal interconnect the digital signal lines should be isolated as much as possible from the analog outputs and other analog circuitry. digital signal lines should not overlay the analog power plane. due to the high clock rates used, avoid long clock lines to the ADV7322 to minimize noise pickup. any active pull-up termination resistors for the digital inputs should be connected to the digital power plane and not the analog power plane. analog signal interconnect locate the ADV7322 as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch.
ADV7322 preliminary technical data rev. pra | page 64 of 88 for optimum performance, the analog outputs should each be source and load terminated, as shown in figure 90. the termination resistors should be as close as possible to the ADV7322 to minimize reflections. for optimum performance, it is recommended that all decoupling and external components relating to the ADV7322 be located on the same side of the pcb and as close as possible to the ADV7322. any unused inputs should be tied to ground. 5k ? v dd_io 5k ? v dd_io comp1, 2 45 v aa 41 v dd v dd_io 1 ADV7322 i 2 c 19 50 49 48 23 clkin_b 63 24 25 33 clkin_a 32 ext_lf 34 unused inputs should be grounded c0?c7 s0?s7 y0?y7 v aa 4.7 f + 4.7k ? 820pf 3.9nf v aa gnd_ io 64 agnd 40 dgnd 11, 57 i 2 cbus 10nf 0.1 f 10nf 0.1 f 10, 56 v dd_io v dd 10nf 1 f v aa + v aa 0.1 f power supply decoupling for each power supply group 36 v aa 0.1 f dac d 39 300 ? dac e 38 300 ? dac f 37 300 ? dac a 44 300 ? dac b 43 300 ? dac c 42 300 ? v ref 46 100nf 1.1k ? v aa recommended external ad1580 for optimum performance 5k ? v dd_io sclk 22 100 ? 680 ? sda 21 alsb 20 r set1 r set2 47 100 ? 3040 ? selection here determines device address 35 3040 ? 5k ? v dd_io s_hsync s_vsync s_blank p_hsync p_vsync p_blank reset 05067-091 figure 90. ADV7322 circuit layout
preliminary technical data ADV7322 rev. pra | page 65 of 88 appendix 1copy generation management system ps cgms data registers 2 to 0 [subaddresses 0x21, 0x22, 0x23] 525p using the vertical blanking interval 525p system, 525p cgms conforms to the cgms-a eia-j cpr1204-1 (march 1998) transfer method of video identification information and to the iec61880 (1998) 525p/60 video systems analog interface for the video and accompanying data. when ps cgms is enabled [subaddress 0x12, bit 6 = 1], cgms data is inserted on line 41. the 525p cgms data registers are at addresses 0x21, 0x22, and 0x23. 625p the 625p cgms conforms to the iec62375 (2004) 625p/50 video systems analog interface for the video and accompanying data using the vertical blanking interval. when ps cgms is enabled [subaddress 0x12, bit 6 = 1], cgms data is inserted on line 43. the 625p cgms data registers are at addresses 0x22, and 0x23. hd cgms [address 0x12, bit 6] the ADV7322 supports copy generation management system (cgms) in hdtv mode (720p and 1080i) in accordance with eiaj cpr-1204-2. the hd cgms data registers are found at addresses 0x021, 0x22, and 0x23. sd cgms data registers 2 to 0 [subaddresses 0x59, 0x5a, 0x5b] the ADV7322 supports copy generation management system (cgms), conforming to the standard. cgms data is transmitted on line 20 of the odd fields and line 283 of even fields. bits c/w05 and c/w06 control whether cgms data is output on odd and even fields. cgms data can be transmitted only when the ADV7322 is configured in ntsc mode. the cgms data is 20 bits long, and the function of each of these bits is as shown in the following table. the cgms data is preceded by a reference pulse of the same amplitude and duration as a cgms bit; see figure 93. function of cgms bits for word 0 to 6 bits, word 1 to 4 bits, and word 2 to 6 bits crc 6 bits, 1 6 + + = x x polynomial crc where default is preset to 111111. 720p system cgms data is applied to line 24 of the luminance vertical blanking interval. 1080i system cgms data is applied to line 19 and line 582 of the luminance vertical blanking interval. cgms functionality if sd cgms crc [address 0x59, bit 4] or ps/hd cgms crc [subaddress 0x12, bit 7] is set to logic 1, the last six bits, c19 to c14, which comprise the 6-bit crc check sequence, are calculated automatically on the ADV7322 based on the lower 14 bits (c0 to c13) of the data in the data registers and output with the remaining 14 bits to form the complete 20 bits of the cgms data. the calculation of the crc sequence is based on the polynomial 6 + x + 1 with a preset value of 111111. if sd cgms crc [address 0x59, bit 4] and ps/hd cgms crc [address 0x12, bit 7] are set to logic 0, all 20 bits (c0 to c19) are output directly from the cgms registers (no crc is calculated, must be calculated by the user).
ADV7322 preliminary technical data rev. pra | page 66 of 88 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 crc sequence ref 5.8 s 0.15 s 6t 0mv ?300mv 70% 10% t = 1/( f h 33) = 963ns f h = horizontal scan frequency t 30ns +700mv bit1 bit2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .bit20 21.2 s 0.22 s 22t 05067-092 c13 c14 c15 c16 c17 c18 c19 figure 91. progressive scan 525p cgms waveform (line 41) r s c0 lsb c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 msb peak white sync level 5 00mv 25mv 5.5 s 0.125 s r = run-in s = start code 13.7 s 05067-093 figure 92. progressive scan 625p cgms-a waveform (line 43) crc sequence ref 0 ire ?40 ire +70 ire +100 ire 05067-094 11.2 s 2.235 s 20ns 49.1 s 0.5 s c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 figure 93. standard definition cgms waveform
preliminary technical data ADV7322 rev. pra | page 67 of 88 crc sequence ref 4t 3.128 s 90ns 17.2 s 160ns 22t t = 1/( f h 1650/58) = 781.93ns f h = horizontal scan frequency 1h t 30ns 0mv ?300mv 70% 10% +700mv bit1 bit2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bit20 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 05067-095 figure 94. hdtv 720p cgms waveform crc sequence ref 4t 4.15 s 60ns 22.84 s 210ns 22t t = 1/(f h 2200/77) = 1.038 s f h = horizontal scan frequency 1h t 30ns 0mv ?300mv 70% 10% +700mv bit1 bit2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bit20 c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 05067-096 figure 95. hdtv 1080i cgms waveform
ADV7322 preliminary technical data rev. pra | page 68 of 88 appendix 2sd wide screen signaling [subaddresses 0x59, 0x5a, 0x5b] the ADV7322 supports wide screen signaling (wss) conforming to the standard. wss data is transmitted on line 23. wss data can be transmitted only when the device is configured in pal mode. the wss data is 14 bits long, and the function of each of these bits is shown in table 38. the wss data is preceded by a run-in sequence and a start code; see figure 95. if sd wss [address 0x59, bit 7] is set to logic 1, it enables the wss data to be transmitted on line 23. the latter portion of line 23 (42.5 s from the falling edge of hsync ) is available for the insertion of video. it is possible to blank the wss portion of line 23 with subaddress 0x61, bit 7. table 38. function of wss bits bit description bit 0 to bit 2 aspect ratio/format/position bit 3 odd parity check of bit 0 to bit 2 b0 b1 b2 b3 aspect ratio format position 0 0 0 1 4:3 full format n/a 1 0 0 0 14:9 letterbox center 0 1 0 0 14:9 letterbox top 1 1 0 1 16:9 letterbox center 0 0 1 0 16:9 letterbox top 1 0 1 1 >16:9 letterbox center 0 1 1 1 14:9 full format center 1 1 1 0 16:9 n/a n/a 1 1 1 0 16:9 b4 0 camera mode 1 film mode b5 0 standard coding 1 motion adaptive color plus b6 0 no helper 1 modulated helper b7 reserved b9 b10 0 0 no open subtitles 1 0 subtitles in active image area 0 1 subtitles out of active image area 1 1 reserved b11 0 no surround sound information 1 surround sound mode b12 reserved b13 reserved active video run-in sequence start code 500mv 11.0 s 38.4 s 42.5 s w0 w1 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 05067-097 figure 96. wss waveform diagram
preliminary technical data ADV7322 rev. pra | page 69 of 88 appendix 3sd closed captioning [subaddresses 0x51 to 0x54] the ADV7322 supports closed captioning conforming to the standard television synchronizing waveform for color transmission. closed captioning is transmitted during the blanked active line time of line 21 of the odd fields and line 284 of the even fields. closed captioning consists of a 7-cycle sinusoidal burst that is frequency and phase locked to the caption data. after the clock run-in signal, the blanking level is held for two data bits and is followed by logic 1 start bit. sixteen bits of data follow the start bit. these consist of two 8-bit bytes, seven data bits, and one odd parity bit. the data for these bytes is stored in the sd closed captioning registers [addresses 0x53 to 0x54]. the ADV7322 also supports the extended closed captioning operation, which is active during even fields and encoded on scan line 284. the data for this operation is stored in the sd closed captioning registers [addresses 0x51 to 0x52]. all clock run-in signals and timing to support closed captioning on lines 21 and 284 are generated automatically by the ADV7322. all pixels inputs are ignored during lines 21 and 284 if closed captioning is enabled. fcc code of federal regulations (cfr) 47 section 15.119 and eia608 describe the closed captioning information for lines 21 and 284. the ADV7322 uses a single buffering method. this means that the closed captioning buffer is only 1 byte deep; therefore, there will be no frame delay in outputting the closed captioning data, unlike other 2-byte-deep buffering systems. the data must be loaded one line before it is output on line 21 and line 284. a typical implementation of this method is to use vsync to interrupt a microprocessor, which in turn will load the new data (two bytes) in every field. if no new data is required for transmission, 0s must be inserted in both data registers; this is called nulling. it is also important to load control codes, all of which are double bytes, on line 21, or a tv will not recognize them. if there is a message like hello world that has an odd number of characters, it is important to pad it out to even to get end of caption 2-byte control code to land in the same field. d0?d6 d0?d6 10.5 0.25 s 12.91 s 7cyclesof 0.5035mhz clock run-in reference color burst (9 cycles) frequency = f sc = 3.579545mhz amplitude = 40 ire 50 ire 40 ire 10.003 s 27.382 s 33.764 s byte 1 byte 0 two 7-bit + parity ascii characters (data) s t a r t p a r i t y p a r i t y 05067-098 figure 97. closed captioning waveform, ntsc
ADV7322 preliminary technical data rev. pra | page 70 of 88 appendix 4test patterns the ADV7322 can generate sd and hd test patterns. ch2 200mv m 10.0 s a ch2 1.20v t 30.6000 s 2 t 05067-099 figure 98. ntsc color bars ch2 200mv m 10.0 s a ch2 1.21v t 30.6000 s 2 t 05067-100 figure 99. pal color bars ch2 100mv m 10.0 s ch2 even t 1.82380ms 2 t 05067-101 figure 100. ntsc black bar [C21 mv, 0 mv, 3.5 mv, 7 mv, 10.5 mv, 14 mv, 18 mv, 23 mv] ch2 100mv m 10.0 s ch2 even t 1.82600ms 2 t 05067-102 figure 101. pal black bar [C21 mv, 0 mv, 3.5 mv, 7 mv, 10.5 mv, 14 mv, 18 mv, 23 mv] ch2 200mv m 4.0 s ch2 even t 1.82944ms 2 t 05067-103 figure 102. 525p hatch pattern ch2 200mv m 4.0 s ch2 even t 1.84208ms 2 t 05067-104 figure 103. 625p hatch pattern
preliminary technical data ADV7322 rev. pra | page 71 of 88 ch2 200mv m 4.0 s ch2 even t 1.82872ms 2 t 05067-105 figure 104. 525p field pattern ch2 200mv m 4.0 s ch2 even t 1.84176ms 2 t 05067-106 figure 105. 625p field pattern ch2 100mv m 4.0 s ch2 even t 1.82936ms 2 t 05067-107 figure 106. 525p black bar [?35 mv, 0 mv, 7 mv, 14 mv, 21 mv, 28 mv, 35 mv] ch2 100mv m 4.0 s ch2 even t 1.84176ms 2 t 05067-108 figure 107. 625p black bar [?35 mv, 0 mv, 7 mv, 14 mv, 21 mv, 28 mv, 5 mv]
ADV7322 preliminary technical data rev. pra | page 72 of 88 the register settings in table 39 are used to generate an sd ntsc cvbs output on dac a, s-video on dacs b and c, and yprpb on dacs d, e, and f. upon power-up, the subcarrier registers are programmed with the appropriate values for ntsc. all other registers are set as normal/default. table 39. ntsc test pattern register writes subaddress register setting 0x00 0xfc 0x40 0x10 0x42 0x40 0x44 0x40 (internal test pattern on) 0x4a 0x08 for pal cvbs output on dac a, the same settings are used, except that subaddress 0x40 is programmed to 0x11 and the fsc registers are programmed as shown in table 40. table 40. pal fsc register writes subaddress description register setting 0x4c fsc0 0xcb 0x4d fsc1 0x8a 0x4e fsc2 0x09 0x4f fsc3 0x2a note that when programming the fsc registers, the user must write the values in the sequence fsc0, fsc1, fsc2, fsc3. the full fsc value to be written is only accepted after the fsc3 write is complete. the register settings in table 41 are used to generate a 525p hatch pattern on dac d, e, and f. all other registers are set as normal/default. table 41. 525p test pattern register writes. subaddress register setting ox00 0xfc 0x01 0x10 0x10 0x00 0x11 0x05 0x16 0xa0 0x17 0x80 0x18 0x80 for 625p hatch pattern on dac d, the same register settings are used except that subaddress 0x10 = 0x18.
preliminary technical data ADV7322 rev. pra | page 73 of 88 appendix 5sd timing modes [subaddress 0x4a] mode 0 (ccir-656)slave option (timing register 0 tr0 = x x x x x 0 0 0) the ADV7322 is controlled by the sav (start active video) and eav (end active video) time codes in the pixel data. all timing information is transmitted using a 4-byte synchronization pattern. a synchronization pattern is sent immediately before and after each line during active picture and retrace. s_vsync , s_hsync , and s_blank (if not used) pins should be tied high during this mode. blank output is available. y c r y f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 f f 0 0 f f a b a b a b 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y c b y c r c b y c b y c r eav code sav code ancillary data (hanc) 4 clock 4 clock 268 clock 1440 clock 4 clock 4 clock 280 clock 1440 clock end of active video line start of active video line analog video input pixels ntsc/pal m system (525 lines/60hz) pal system (625 lines/50hz) y 05067-109 figure 108. sd slave mode 0
ADV7322 preliminary technical data rev. pra | page 74 of 88 mode 0 (ccir-656)master option (timing register 0 tr0 = x x x x x 0 0 1) the ADV7322 generates h, v, and f signals required for the sav (start active video) and eav (end active video) time codes in the ccir656 standard. the h bit is output on s_hsync , the v bit is output on s_blank , and the f bit is output on s_vsync . 522 523 524 525 8 9 10 11 20 21 22 display display vertical blank odd field even field h v f 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank h v f 05067-110 7 6 5 4 3 2 1 figure 109. sd master mode 0, ntsc
preliminary technical data ADV7322 rev. pra | page 75 of 88 622 623 624 625 21 22 23 display display vertical blank h v f odd field even field 309 310 311 312 314 315 316 317 318 319 320 334 335 336 display display vertical blank h v f odd field even field 313 05067-111 7 6 5 4 3 2 1 figure 110. sd master mode 0, pal a nalo g video h f v 05067-112 figure 111. sd master mode 0, data transitions
ADV7322 preliminary technical data rev. pra | page 76 of 88 mode 1slave option (timing register 0 tr0 = x x x x x 0 1 0) in this mode, the ADV7322 accepts horizontal sync and odd/even field signals. when hsync is low, a transition of the field input indicates a new frame, i.e., vertical retrace. the blank signal is optional. when the blank input is disabled, ADV7322 automatically blanks all normally blank lines as per ccir-624. hsync is input on s_hsync , blank on s_blank , and field on s_vsync . 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank 522 523 524 525 59 10 11 20 21 22 display display vertical blank odd field even field field field hsync blank hsync blank 05067-113 7 6 4 3 2 1 8 figure 112. sd slave mode 1 (ntsc)
preliminary technical data ADV7322 rev. pra | page 77 of 88 mode 1master option (timing register 0 tr0 = x x x x x 0 1 1) in this mode, the ADV7322 can generate horizontal sync and odd/even field signals. when hsync is low, a transition of the field input indicates a new frame, i.e., vertical retrace. the blank signal is optional. when the blank input is disabled, ADV7322 automatically blanks all normally blank lines as per ccir-624. pixel data is latched on the rising clock edge following the timing signal transitions. hsync is output on the s_hsync , blank on s_blank , and field on s_vsync . 622 623 624 625 21 22 23 display vertical blank odd field even field field display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display vertical blank odd field even field display 320 field 5 7 6 4 3 2 1 hsync blank hsync blank 05067-114 figure 113. sd slave mode 1 (pal) field pixel data pal = 12 clock/2 ntsc = 16 clock/2 cb y cr y hsync blank pal = 132 clock/2 ntsc = 122 clock/2 05067-115 figure 114. sd timing mode 1odd/ even field transitions master/slave
ADV7322 preliminary technical data rev. pra | page 78 of 88 mode 2 slave option (timing register 0 tr0 = x x x x x 1 0 0) in this mode, the ADV7322 accepts horizontal and vertical sync signals. a coincident low transition of both hsync and vsync inputs indicates the start of an odd field. a vsync low transition when hsync is high indicates the start of an even field. the blank signal is optional. when the blank input is disabled, ADV7322 automatically blanks all normally blank lines as per ccir-624. hsync is input on s_hsync , blank on s_blank , and vsync on s_vsync . 522 523 524 525 9 10 11 20 21 22 display display vertical blank odd field even field 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank 5 7 6 4 3 2 1 8 hsync blank vsync hsync blank vsync 05067-116 figure 115. sd slave mode 2 (ntsc) 622 623 624 625 21 22 23 display vertical blank odd field even field display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display vertical blank odd field even field display 320 7 6 5 4 3 2 1 hsync blank vsync hsync blank vsync 05067-117 figure 116. sd slave mode 2 (pal)
preliminary technical data ADV7322 rev. pra | page 79 of 88 mode 2master option (timing register 0 tr0 = x x x x x 1 0 1) in this mode, the ADV7322 can generate horizontal and vertical sync signals. a coincident low transition of both hsync and vsync inputs indicates the start of an odd field. a vsync low transition when hsync is high indicates the start of an even field. the blank signal is optional. when the blank input is disabled, the ADV7322 automatically blanks all normally blank lines as per ccir-624. hsync is output on s_hsync , blank on s_blank , and vsync on s_vsync . cb y 05067-118 pixel data hsync blank vsync pal = 12 clock/2 ntsc = 16 clock/2 pal = 132 clock/2 ntsc = 122 clock/2 y cr figure 117. sd timing mode 2 even-t o-odd field transition master/slave cb pixel data hsync blank vsync pal = 12 clock/2 ntsc = 16 clock/2 pal = 132 clock/2 ntsc = 122 clock/2 pal = 864 clock/2 ntsc = 858 clock/2 cb y y cr 05067-119 figure 118. sd timing mode 2 odd-to-even field transition
ADV7322 preliminary technical data rev. pra | page 80 of 88 mode 3master/slave option (timing register 0 tr0 = x x x x x 1 1 0 or x x x x x 1 1 1) in this mode, the ADV7322 accepts or generates horizontal sync and odd/even field signals. when hsync is high, a transition of the field input indicates a new frame, i.e., vertical retrace. the blank signal is optional. when the blank input is disabled, ADV7322 automatically blanks all normally blank lines as per ccir-624. hsync is output in master mode and input in slave mode on s_vsync , blank on s_blank , and vsync on s_vsync . 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank 522 523 524 525 9 10 11 20 21 22 display display vertical blank odd field even field hsync blank field 05067-120 hsync blank field 8 7 6 5 4 3 2 1 figure 119. sd timing mode 3 (ntsc) 622 623 624 625 5 6212223 display vertical blank odd field even field field display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display vertical blank odd field even field field display 320 4 3 2 1 7 hsync blank hsync blank 05067-121 figure 120. sd timing mode 3 (pal)
preliminary technical data ADV7322 rev. pra | page 81 of 88 appendix 6hd timing vertical blanking interval display 1124 1125 1 2 5 6 7 8 21 4 3 20 22 560 field 1 field 2 vertical blanking interval display 561 562 563 564 567 568 569 570 584 566 565 583 585 1123 p_hsync p_vsync p_hsync p_vsync 05067-122 figure 121. 1080i hsync and vsync input timing
ADV7322 preliminary technical data rev. pra | page 82 of 88 appendix 7video output levels hd yprpb output levels input code 940 64 eia-770.2, standard for y output voltage 300mv 700mv 700mv 960 64 eia-770.2, standard for pr/pb output voltage 512 05067-123 figure 122. eia 770.2 standard output signals (525p/625p) 782mv 714mv 286mv 700mv input code 940 64 eia-770.1, standard for y output voltage 960 64 eia-770.1, standard for pr/pb output voltage 512 05067-124 figure 123. eia 770.1 standard output signals (525p/625p) 300mv input code 940 64 eia-770.3, standard for y output voltage 700mv 700mv 600mv 960 64 eia-770.3, standard for pr/pb output voltage 512 05067-125 figure 124. eia 770.3 standard output signals (1080i/720p) 300mv 300mv 700mv 700mv input code 1023 64 y?output levels for full input selection output voltage 1023 64 pr/pb?output levels for full input selection output voltage input code 05067-126 figure 125. output levels for full input selection
preliminary technical data ADV7322 rev. pra | page 83 of 88 rgb output levels pattern: 100%/75% color bars 3 00mv 3 00mv 3 00mv 700mv 700mv 525mv 525mv 700mv 525mv 05067-127 figure 126. ps rgb output levels 3 00mv 0mv 3 00mv 0mv 3 00mv 0mv 700mv 525mv 700mv 525mv 700mv 525mv 05067-128 figure 127. ps rgb output levelsrgb sync enabled 300mv 300mv 300mv 700mv 700mv 525mv 525mv 700mv 525mv 05067-129 figure 128. sd rgb output levelsrgb sync disabled 300mv 0mv 300mv 0mv 300mv 0mv 700mv 525mv 700mv 525mv 700mv 525mv 05067-130 figure 129. sd rgb output levelsrgb sync enabled
ADV7322 preliminary technical data rev. pra | page 84 of 88 yprpb levelssmpte/ebu n10 pattern: 100% color bars white yellow cyan green magenta red blue black 700mv 05067-131 figure 130. pb levelsntsc white yellow cyan green magenta red blue black 700mv 0 5 0 6 7 - 1 3 2 figure 131. pb levelspal white yellow cyan green magent a red blue black 700mv 05067-133 figure 132. pr levelsntsc white yellow cyan green magent a red blue black 700mv 05067-134 figure 133. pr levelspal 300mv 700mv white yellow cyan green magent a red blue black 05067-135 figure 134. y levelsntsc 700mv 300mv white yellow cyan green magent a red blue black 05067-136 figure 135. y levelspal
preliminary technical data ADV7322 rev. pra | page 85 of 88 0.5 0 apl = 44.5% 525 line ntsc slow clamp to 0.00v at 6.72 s 10 20 f1 l76 30 40 50 60 100 50 0 ?50 0 volts ire:flt microseconds precision mode off synchronous sync = a frames selected 1, 2 05067-137 figure 136. ntsc color bars 75% 05067-138 0 noise reduction: 15.05db apl needs sync-source. 525 line ntsc no filtering slow clamp to 0.00 at 6.72 s 10 20 f1 l76 30 40 50 60 50 ?50 0 0.4 0.2 0 ?0.2 ?0.4 microseconds precision mode off synchronous sync = b frames selected 1, 2 volts ire:flt figure 137. ntsc chroma 05067-139 noise reduction: 15.05db apl = 44.3% 525 line ntsc no filtering slow clamp to 0.00 at 6.72 s 10 20 f2 l238 30 40 50 60 50 0 0 0.4 0.2 0.6 0 ?0.2 microseconds precision mode off synchronous sync = source frames selected 1, 2 volts ire:flt figure 138. ntsc luma 05067-140 volts noise reduction: 0.00db apl = 39.1% 625 line ntsc no filtering slow clamp to 0.00 at 6.72 s 10 020 l608 30 40 50 60 0.4 0.2 0.6 0 ?0.2 microseconds precision mode off synchronous sound-in-sync off frames selected 1, 2, 3, 4 figure 139. pal color bars 75% 05067-141 volts apl needs sync-source. 625 line pal no filtering slow clamp to 0.00 at 6.72 s 10 20 l575 30 40 50 60 0 0.5 ?0.5 microseconds no bunch signal precision mode off synchronous sound-in-sync off frames selected 1 figure 140. pal chroma 05067-142 volts apl needs sync-source. 625 line pal no filtering slow clamp to 0.00 at 6.72 s 10 020 l575 30 40 50 60 0 0.5 microseconds no bunch signal precision mode off synchronous sound-in-sync off frames selected 1 70 figure 141. pal luma
ADV7322 preliminary technical data rev. pra | page 86 of 88 appendix 8video standards f v h* f f 272t 4t *1 4t 1920t eav code sav code digital active line 4 clock 4 clock 2112 2116 2156 2199 0 44 188 192 2111 0 0 0 0 0 0 0 0 f f f v h* c b c r c r y y fvh* = fvh and parity bits sav/eav: line 1?562: f = 0 sav/eav: line 563?1125: f = 1 sav/eav: line 1?20; 561?583; 1124?1125: v = 1 sav/eav: line 21?560; 584?1123: v = 0 for a frame rate of 30hz: 40 samples for a frame rate of 25hz: 480 samples input pixels analog waveform sample number smpte 274m digital horizontal blanking ancillary data (optional) or blanking code 0 h datum 05067-143 figure 142. eav/sav input data timing diagramsmpte 274m y eav code ancillary data (optional) sav code digital active line 719 723 736 799 853 0 fvh* = fvh and parity bits sav: line 43?525 = 200h sav: line 1?42 = 2ac eav: line 43?525 = 274h eav: line 1?42 = 2d8 4 clock 4 clock 857 719 0 h datum digital horizontal blanking 0 0 0 0 0 0 0 0 c b c r c r y y f v h* smpte 293m input pixels a nalog wavefor m sample number f f f f f v h* 05067-144 figure 143. eav/sav input data timing diagramsmpte 293m
preliminary technical data ADV7322 rev. pra | page 87 of 88 vertical blank 52252352452512567891213141516424344 active video active video 05067-145 figure 144. smpte 293m (525p) 622 623 624 625 10 11 43 44 45 4 vertical blank active video active video 12 56789 12 13 05067-146 figure 145. itu-r bt.1358 (625p) 747 748 749 750 26 27 25 744 745 display vertical blanking interval 12 3 45 67 8 05067-147 figure 146. smpte 296m (720p) display 1124 1125 21 4 3 20 22 560 field 1 display 561 562 563 564 567 568 569 570 584 566 565 583 585 1123 field 2 vertical blanking interval vertical blanking interval 12 5678 05067-148 figure 147. smpte 274m (1080i)
ADV7322 preliminary technical data rev. pra | page 88 of 88 outline dimensions top view (pins down) 1 16 17 33 32 48 49 64 0.27 0.22 0.17 0.50 bsc 10.00 bsc sq 1.60 max seating plane 0.75 0.60 0.45 view a 12.00 bsc sq 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 10 6 2 7 3.5 0 0.15 0.05 pin 1 compliant to jedec standards ms-026bcd figure 148. 64-lead low profile quad flat package [lqfp] (st-64-2) dimensions shown in millimeters ordering guide model package description package option ADV7322kstz 1 64-lead low profile quad flat package [lqfp] st-64-2 eval-ADV7322eb evaluation board 1 z = pb-free part. ? 2004 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr05135C0C9/04(pra)

▲Up To Search▲

Price & Availability of ADV7322

	To Download ADV7322 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .